An all-digital PLL clock multiplier
(2002) 2002 IEEE Asia-Pacific Conference on ASIC. Proceedings p.275-278- Abstract
- A fully integrated digital PLL used as a clock multiplying circuit is designed and manufactured. The PLL has no off-chip components and it is made from standard cells found in most digital standard cell libraries. It is therefore portable between processes as an IP-block. Using a 0.35 μm standard CMOS process and a 3.0 V supply voltage, the PLL has a frequency range of 152 MHz to 366 MHz and occupies an on-chip area of about 0.07 mm<sup>2</sup>. In addition, the next version of this all-digital PLL is described in synthesizable VHDL-code, which simplifies digital system process change simulation
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/611666
- author
- Olsson, Thomas LU and Nilsson, Peter LU
- organization
- publishing date
- 2002
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- CMOS all-digital PLL clock multipliers, clock multiplying circuits, off-chip components, digital standard cell libraries, process portable IP-blocks, CMOS process, PLL supply voltage, PLL frequency range, synthesizable VHDL code, PLL on-chip area, integrated digital PLL, 152 to 366 MHz, 3.0 V, digital system process change simulation, 0.35 micron
- host publication
- 2002 IEEE Asia-Pacific Conference on ASIC. Proceedings (Cat. No.02EX547)
- pages
- 275 - 278
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- 2002 IEEE Asia-Pacific Conference on ASIC. Proceedings
- conference location
- Taipei, Taiwan
- conference dates
- 2002-08-06 - 2002-08-08
- external identifiers
-
- wos:000180272700069
- scopus:84966309399
- ISBN
- 0-7803-7363-4
- DOI
- 10.1109/APASIC.2002.1031585
- language
- English
- LU publication?
- yes
- id
- 938e3dec-4647-423e-9a92-b5d2c9dc5b4f (old id 611666)
- date added to LUP
- 2016-04-04 12:20:11
- date last changed
- 2022-01-29 23:14:16
@inproceedings{938e3dec-4647-423e-9a92-b5d2c9dc5b4f, abstract = {{A fully integrated digital PLL used as a clock multiplying circuit is designed and manufactured. The PLL has no off-chip components and it is made from standard cells found in most digital standard cell libraries. It is therefore portable between processes as an IP-block. Using a 0.35 μm standard CMOS process and a 3.0 V supply voltage, the PLL has a frequency range of 152 MHz to 366 MHz and occupies an on-chip area of about 0.07 mm<sup>2</sup>. In addition, the next version of this all-digital PLL is described in synthesizable VHDL-code, which simplifies digital system process change simulation}}, author = {{Olsson, Thomas and Nilsson, Peter}}, booktitle = {{2002 IEEE Asia-Pacific Conference on ASIC. Proceedings (Cat. No.02EX547)}}, isbn = {{0-7803-7363-4}}, keywords = {{CMOS all-digital PLL clock multipliers; clock multiplying circuits; off-chip components; digital standard cell libraries; process portable IP-blocks; CMOS process; PLL supply voltage; PLL frequency range; synthesizable VHDL code; PLL on-chip area; integrated digital PLL; 152 to 366 MHz; 3.0 V; digital system process change simulation; 0.35 micron}}, language = {{eng}}, pages = {{275--278}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{An all-digital PLL clock multiplier}}, url = {{http://dx.doi.org/10.1109/APASIC.2002.1031585}}, doi = {{10.1109/APASIC.2002.1031585}}, year = {{2002}}, }