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A 10-bit, 100-MHz CMOS linear interpolation DAC

Yijun, Zhou LU and Yuan, Jiren LU (2002) ESSCIRC 2002. Proceedings of the 28th European Solid-State Circuit Conference In ESSCIRC 2002. Proceedings of the 28th European Solid-State Circuit Conference p.471-474
Abstract
A 10-bit, 100-MHz CMOS linear interpolation digital-to-analog converter (DAC) is presented. It includes a 16-tap voltage controlled delay line and a 10-bit binary-weighted DAC with a time-interleaved structure. The linear interpolation not only increases the attenuation of the DAC's image components, but also reduces the glitch of the binary-weighted DAC. The requirement for the analog reconstruction filter is therefore greatly relaxed. The DAC is optimized for the single chip design of wire or wireless transmitters. The chip was fabricated in a standard 3.3 V, 0.35 μm, double-poly, triple-metal digital CMOS process. The core size of the chip is 0.49 mm × 0.52 mm, and power consumption is 86.5 mW with a 3.3 V power supply. The attenuation... (More)
A 10-bit, 100-MHz CMOS linear interpolation digital-to-analog converter (DAC) is presented. It includes a 16-tap voltage controlled delay line and a 10-bit binary-weighted DAC with a time-interleaved structure. The linear interpolation not only increases the attenuation of the DAC's image components, but also reduces the glitch of the binary-weighted DAC. The requirement for the analog reconstruction filter is therefore greatly relaxed. The DAC is optimized for the single chip design of wire or wireless transmitters. The chip was fabricated in a standard 3.3 V, 0.35 μm, double-poly, triple-metal digital CMOS process. The core size of the chip is 0.49 mm × 0.52 mm, and power consumption is 86.5 mW with a 3.3 V power supply. The attenuation of image components is doubled (dB) compared with the conventional DAC (Less)
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author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
digital-to-analog converter, CMOS linear interpolation DAC, 16-tap voltage controlled delay line, binary-weighted DAC, time-interleaved structure, analog reconstruction filter, wire transmitters, wireless transmitters, digital CMOS process, double-poly triple-metal CMOS process, 10 bit, 100 MHz, 3.3 V, 0.35 micron, 86.5 mW
in
ESSCIRC 2002. Proceedings of the 28th European Solid-State Circuit Conference
pages
471 - 474
publisher
Univ. Bologna
conference name
ESSCIRC 2002. Proceedings of the 28th European Solid-State Circuit Conference
external identifiers
  • Scopus:84893813991
ISBN
88-900847-9-0
language
English
LU publication?
yes
id
d6f9ac5e-8bad-4dc1-bbb4-761b2b8dadac (old id 611876)
date added to LUP
2007-11-29 13:09:08
date last changed
2017-02-19 04:31:44
@inproceedings{d6f9ac5e-8bad-4dc1-bbb4-761b2b8dadac,
  abstract     = {A 10-bit, 100-MHz CMOS linear interpolation digital-to-analog converter (DAC) is presented. It includes a 16-tap voltage controlled delay line and a 10-bit binary-weighted DAC with a time-interleaved structure. The linear interpolation not only increases the attenuation of the DAC's image components, but also reduces the glitch of the binary-weighted DAC. The requirement for the analog reconstruction filter is therefore greatly relaxed. The DAC is optimized for the single chip design of wire or wireless transmitters. The chip was fabricated in a standard 3.3 V, 0.35 μm, double-poly, triple-metal digital CMOS process. The core size of the chip is 0.49 mm × 0.52 mm, and power consumption is 86.5 mW with a 3.3 V power supply. The attenuation of image components is doubled (dB) compared with the conventional DAC},
  author       = {Yijun, Zhou and Yuan, Jiren},
  booktitle    = {ESSCIRC 2002. Proceedings of the 28th European Solid-State Circuit Conference},
  isbn         = {88-900847-9-0},
  keyword      = {digital-to-analog converter,CMOS linear interpolation DAC,16-tap voltage controlled delay line,binary-weighted DAC,time-interleaved structure,analog reconstruction filter,wire transmitters,wireless transmitters,digital CMOS process,double-poly triple-metal CMOS process,10 bit,100 MHz,3.3 V,0.35 micron,86.5 mW},
  language     = {eng},
  pages        = {471--474},
  publisher    = {Univ. Bologna},
  title        = {A 10-bit, 100-MHz CMOS linear interpolation DAC},
  year         = {2002},
}