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A 2048 complex point FFT processor using a novel data scaling approach

Lenart, Thomas LU and Öwall, Viktor LU (2003) IEEE International Symposium on Circuits and Systems (ISCAS '03), 2003 4. p.45-48
Abstract
In this paper, a novel data scaling method for pipelined FFT processors is proposed. By using data scaling, the FFT processor can operate on a wide range of input signals without performance loss. Compared to existing block scaling methods, like implementations of Convergent Block Floating Point (CBFP), the memory requirements can be reduced while preserving the SNR. The FFT processor has been synthesized and sent for fabrication in a 0.35μm standard CMOS technology. In netlist simulations, the FFT processor is capable of calculating a 2048 complex point FFT or IFFT in 27μs with a maximum clock frequency of 76MHz.
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
Data scaling
host publication
Proceedings - IEEE International Symposium on Circuits and Systems
volume
4
pages
45 - 48
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
IEEE International Symposium on Circuits and Systems (ISCAS '03), 2003
conference location
Bangkok, Thailand
conference dates
2003-05-25 - 2003-05-28
external identifiers
  • wos:000184904400012
  • other:CODEN: PICSDI
  • scopus:18144450336
ISSN
2158-1525
0271-4310
DOI
10.1109/ISCAS.2003.1205769
language
English
LU publication?
yes
id
39502cdf-f928-4ac8-bd86-c4db08dab7b6 (old id 611993)
date added to LUP
2016-04-01 12:04:17
date last changed
2020-01-12 09:09:15
@inproceedings{39502cdf-f928-4ac8-bd86-c4db08dab7b6,
  abstract     = {In this paper, a novel data scaling method for pipelined FFT processors is proposed. By using data scaling, the FFT processor can operate on a wide range of input signals without performance loss. Compared to existing block scaling methods, like implementations of Convergent Block Floating Point (CBFP), the memory requirements can be reduced while preserving the SNR. The FFT processor has been synthesized and sent for fabrication in a 0.35μm standard CMOS technology. In netlist simulations, the FFT processor is capable of calculating a 2048 complex point FFT or IFFT in 27μs with a maximum clock frequency of 76MHz.},
  author       = {Lenart, Thomas and Öwall, Viktor},
  booktitle    = {Proceedings - IEEE International Symposium on Circuits and Systems},
  issn         = {2158-1525},
  language     = {eng},
  pages        = {45--48},
  publisher    = {IEEE - Institute of Electrical and Electronics Engineers Inc.},
  title        = {A 2048 complex point FFT processor using a novel data scaling approach},
  url          = {http://dx.doi.org/10.1109/ISCAS.2003.1205769},
  doi          = {10.1109/ISCAS.2003.1205769},
  volume       = {4},
  year         = {2003},
}