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FPGA implementation of controller-datapath pair in custom image processor design

Jiang, Hongtu LU and Öwall, Viktor LU (2004) IEEE International Symposium on Circuits and Systems (ISCAS), 2004 In Proceedings of the 2004 International Symposium on Circuits and Systems 5. p.141-144
Abstract
In order to reduce the effort of the controller design in the customized image convolution processor, a controller synthesis tool is developed based on [9] to support the design flow from a system or algorithm specification to RTL level VHDL. Architecture extensions to basic FSMs structures are implemented with the purpose of optimizing controller design for area and power consumption. Together with controller implementation, a custom datapath architecture with three level memory hierarchies is developed aiming at a real-time power efficient image processing solution with low I/O bandwidth requirements. The complete design is prototyped on Xilinx Virtex 2 platform with comparable performance with that of TI C64x processor at only 2/15 of... (More)
In order to reduce the effort of the controller design in the customized image convolution processor, a controller synthesis tool is developed based on [9] to support the design flow from a system or algorithm specification to RTL level VHDL. Architecture extensions to basic FSMs structures are implemented with the purpose of optimizing controller design for area and power consumption. Together with controller implementation, a custom datapath architecture with three level memory hierarchies is developed aiming at a real-time power efficient image processing solution with low I/O bandwidth requirements. The complete design is prototyped on Xilinx Virtex 2 platform with comparable performance with that of TI C64x processor at only 2/15 of its clock frequency. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
Line memories, Image processors, Clock cycles, Image size
in
Proceedings of the 2004 International Symposium on Circuits and Systems
volume
5
pages
141 - 144
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
IEEE International Symposium on Circuits and Systems (ISCAS), 2004
external identifiers
  • wos:000223103900036
  • scopus:4344705192
ISSN
2158-1525
0271-4310
language
English
LU publication?
yes
id
5f93f3d2-6eee-44ad-97ff-3fc087d49335 (old id 613575)
alternative location
http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=1329482
date added to LUP
2007-11-26 19:58:14
date last changed
2017-01-01 04:58:13
@inproceedings{5f93f3d2-6eee-44ad-97ff-3fc087d49335,
  abstract     = {In order to reduce the effort of the controller design in the customized image convolution processor, a controller synthesis tool is developed based on [9] to support the design flow from a system or algorithm specification to RTL level VHDL. Architecture extensions to basic FSMs structures are implemented with the purpose of optimizing controller design for area and power consumption. Together with controller implementation, a custom datapath architecture with three level memory hierarchies is developed aiming at a real-time power efficient image processing solution with low I/O bandwidth requirements. The complete design is prototyped on Xilinx Virtex 2 platform with comparable performance with that of TI C64x processor at only 2/15 of its clock frequency.},
  author       = {Jiang, Hongtu and Öwall, Viktor},
  booktitle    = {Proceedings of the 2004 International Symposium on Circuits and Systems},
  issn         = {2158-1525},
  keyword      = {Line memories,Image processors,Clock cycles,Image size},
  language     = {eng},
  pages        = {141--144},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {FPGA implementation of controller-datapath pair in custom image processor design},
  volume       = {5},
  year         = {2004},
}