Skip to main content

Lund University Publications

LUND UNIVERSITY LIBRARIES

Reduced transceiver-delay for OFDM systems

Kristensen, Fredrik LU ; Nilsson, Peter LU and Olsson, Anders (2004) IEEE Vehicular Technology Conference, VTC Spring, 2004 p.1242-1245
Abstract
In this paper, it is shown that more than half of the data flow buffer, due to a bit reversed FFT output and cyclic prefix in an OFDM transceiver, can be removed. To achieve this, a new pipelined FFT processor is proposed and a cyclic suffix is used instead of the more commonly used cyclic prefix. The FFT processor is used either with a forward or backward data flow, i.e. performing either a decimation in time or a decimation in frequency FFT. However, this approach precludes wordlength optimization in the processor and therefore a semi floating-point arithmetic is used to achieve high signal-to-noise ratio. Total delay through the transceiver is reduced by 25% and for larger transceivers silicon area is reduced by as much as 25%. In... (More)
In this paper, it is shown that more than half of the data flow buffer, due to a bit reversed FFT output and cyclic prefix in an OFDM transceiver, can be removed. To achieve this, a new pipelined FFT processor is proposed and a cyclic suffix is used instead of the more commonly used cyclic prefix. The FFT processor is used either with a forward or backward data flow, i.e. performing either a decimation in time or a decimation in frequency FFT. However, this approach precludes wordlength optimization in the processor and therefore a semi floating-point arithmetic is used to achieve high signal-to-noise ratio. Total delay through the transceiver is reduced by 25% and for larger transceivers silicon area is reduced by as much as 25%. In addition, the proposed scheme reduces the required amount of memory accesses to insert a cyclic extension, and has the basic properties of a simple interleaver (Less)
Please use this url to cite or link to this publication:
author
; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
silicon area reduction, memory accesses reduction, cyclic extension insertion, semi floating-point arithmetic, frequency decimation, time decimation, backward data flow, forward data flow, cyclic suffix, pipelined FFT processor, bit reversed FFT output, cyclic prefix, interleaver, data flow buffer, high signal-to-noise ratio, transceiver delay reduction, OFDM transceiver
host publication
2004 IEEE 59th Vehicular Technology Conference. VTC 2004-Spring
pages
1242 - 1245
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
IEEE Vehicular Technology Conference, VTC Spring, 2004
conference location
Milan, Italy
conference dates
2004-05-17 - 2004-05-19
external identifiers
  • wos:000226279400257
  • scopus:15344351633
ISBN
0-7803-8255-2
DOI
10.1109/VETECS.2004.1390451
language
English
LU publication?
yes
id
443ca542-7d70-48c8-be71-9c437071d301 (old id 614765)
date added to LUP
2016-04-04 10:11:30
date last changed
2022-01-29 19:53:46
@inproceedings{443ca542-7d70-48c8-be71-9c437071d301,
  abstract     = {{In this paper, it is shown that more than half of the data flow buffer, due to a bit reversed FFT output and cyclic prefix in an OFDM transceiver, can be removed. To achieve this, a new pipelined FFT processor is proposed and a cyclic suffix is used instead of the more commonly used cyclic prefix. The FFT processor is used either with a forward or backward data flow, i.e. performing either a decimation in time or a decimation in frequency FFT. However, this approach precludes wordlength optimization in the processor and therefore a semi floating-point arithmetic is used to achieve high signal-to-noise ratio. Total delay through the transceiver is reduced by 25% and for larger transceivers silicon area is reduced by as much as 25%. In addition, the proposed scheme reduces the required amount of memory accesses to insert a cyclic extension, and has the basic properties of a simple interleaver}},
  author       = {{Kristensen, Fredrik and Nilsson, Peter and Olsson, Anders}},
  booktitle    = {{2004 IEEE 59th Vehicular Technology Conference. VTC 2004-Spring}},
  isbn         = {{0-7803-8255-2}},
  keywords     = {{silicon area reduction; memory accesses reduction; cyclic extension insertion; semi floating-point arithmetic; frequency decimation; time decimation; backward data flow; forward data flow; cyclic suffix; pipelined FFT processor; bit reversed FFT output; cyclic prefix; interleaver; data flow buffer; high signal-to-noise ratio; transceiver delay reduction; OFDM transceiver}},
  language     = {{eng}},
  pages        = {{1242--1245}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  title        = {{Reduced transceiver-delay for OFDM systems}},
  url          = {{http://dx.doi.org/10.1109/VETECS.2004.1390451}},
  doi          = {{10.1109/VETECS.2004.1390451}},
  year         = {{2004}},
}