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A low complexity architecture for binary image erosion and dilation using structuring element decomposition

Hedberg, Hugo LU ; Kristensen, Fredrik LU ; Nilsson, Peter LU and Öwall, Viktor LU (2005) IEEE International Symposium on Circuits and Systems (ISCAS), 2005 In IEEE International Symposium on Circuits and Systems (ISCAS) p.3431-3434
Abstract
This paper describes a new hardware architecture for binary image erosion and dilation. The design is to be used in a self contained real-time surveillance system. Thus, low complexity and low power consumption are main constraints. To achieve this goal the aim has been to reduce memory requirements and the number of memory accesses per pixel. By storing only the number of consecutive ones that appears horizontally and vertically in the input image, only two internal memory accesses per calculated output pixel are required. The number of memory accesses is independent of the size of the structuring element (SE) as long as it is rectangular and only contains ones, which is a common case. The internal memory size is proportional to... (More)
This paper describes a new hardware architecture for binary image erosion and dilation. The design is to be used in a self contained real-time surveillance system. Thus, low complexity and low power consumption are main constraints. To achieve this goal the aim has been to reduce memory requirements and the number of memory accesses per pixel. By storing only the number of consecutive ones that appears horizontally and vertically in the input image, only two internal memory accesses per calculated output pixel are required. The number of memory accesses is independent of the size of the structuring element (SE) as long as it is rectangular and only contains ones, which is a common case. The internal memory size is proportional to log<sub>2</sub>(SE<sub>height</sub>), which means that a large span of SE sizes can be supported with a small amount of hardware (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
structuring element decomposition, memory accesses per pixel, reduced memory requirements, power consumption, real-time surveillance system, image dilation, hardware architecture, low complexity architecture, binary image erosion
in
IEEE International Symposium on Circuits and Systems (ISCAS)
pages
3431 - 3434
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
IEEE International Symposium on Circuits and Systems (ISCAS), 2005
external identifiers
  • WOS:000232002403104
  • Scopus:54749087852
ISBN
0-7803-8834-8
DOI
10.1109/ISCAS.2005.1465366
language
English
LU publication?
yes
id
35b6b579-c3b0-4031-b376-11100e82d949 (old id 616130)
date added to LUP
2007-11-25 11:29:36
date last changed
2017-01-01 08:00:21
@inproceedings{35b6b579-c3b0-4031-b376-11100e82d949,
  abstract     = {This paper describes a new hardware architecture for binary image erosion and dilation. The design is to be used in a self contained real-time surveillance system. Thus, low complexity and low power consumption are main constraints. To achieve this goal the aim has been to reduce memory requirements and the number of memory accesses per pixel. By storing only the number of consecutive ones that appears horizontally and vertically in the input image, only two internal memory accesses per calculated output pixel are required. The number of memory accesses is independent of the size of the structuring element (SE) as long as it is rectangular and only contains ones, which is a common case. The internal memory size is proportional to log&lt;sub&gt;2&lt;/sub&gt;(SE&lt;sub&gt;height&lt;/sub&gt;), which means that a large span of SE sizes can be supported with a small amount of hardware},
  author       = {Hedberg, Hugo and Kristensen, Fredrik and Nilsson, Peter and Öwall, Viktor},
  booktitle    = {IEEE International Symposium on Circuits and Systems (ISCAS)},
  isbn         = {0-7803-8834-8},
  keyword      = {structuring element decomposition,memory accesses per pixel,reduced memory requirements,power consumption,real-time surveillance system,image dilation,hardware architecture,low complexity architecture,binary image erosion},
  language     = {eng},
  pages        = {3431--3434},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {A low complexity architecture for binary image erosion and dilation using structuring element decomposition},
  url          = {http://dx.doi.org/10.1109/ISCAS.2005.1465366},
  year         = {2005},
}