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Modelling and Implementation of a vision system for embedded systems

Andersson, Per LU (2003)
Abstract
Today more and more functionality is included in embedded systems, resulting in an increased system complexity. existing design methodologies and design tools are not adequate to deal with this increase in complexity. To overcome these limitations application specific design solutions are more common. In this thesis we presents such solutions for real-time image processing. This work is part of the WITAS Unmanned Aerial Vehicle (UAV) project. Within this project we are developing a prototype UAV.



We introduce Image Processing Data Flow Graph (IP-DFG), a data flow based computational model that is suitable for modelling complex image processing algorithms. We also present IPAPI, a run-time system based on IP-DFG. We use... (More)
Today more and more functionality is included in embedded systems, resulting in an increased system complexity. existing design methodologies and design tools are not adequate to deal with this increase in complexity. To overcome these limitations application specific design solutions are more common. In this thesis we presents such solutions for real-time image processing. This work is part of the WITAS Unmanned Aerial Vehicle (UAV) project. Within this project we are developing a prototype UAV.



We introduce Image Processing Data Flow Graph (IP-DFG), a data flow based computational model that is suitable for modelling complex image processing algorithms. We also present IPAPI, a run-time system based on IP-DFG. We use IPAPI for early evaluation of image processing algorithms for the vision subsystem of the WITAS UAV prototype. This is carried out via co-simulation of IPAPI with the other subsystems, such as the reasoning subsystem and helicopter control subsystem. We also show how IPAPI can be used as a framework to derive an optimised implementation for the on-board system.



FPGAs can be used to accelerate the image processing operations. Time multiplexed FPGAs (TMFPGAs) have shown potential in both reducing the price of FPGAs and in hiding the reconfiguration time for dynamically reconfigured FPGAs. To use a TMFPGA, the operation must be temporally partitioned. We present an algorithm that does temporal

partitioning on a technology mapped net-list. This makes it possible to use excising design tools when developing for TMFPGAs. (Less)
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English
LU publication?
yes
id
e68947a9-c8df-48f4-9bc7-cdf75b70cd0e (old id 637368)
date added to LUP
2007-12-04 10:02:18
date last changed
2016-09-19 08:45:00
@misc{e68947a9-c8df-48f4-9bc7-cdf75b70cd0e,
  abstract     = {Today more and more functionality is included in embedded systems, resulting in an increased system complexity. existing design methodologies and design tools are not adequate to deal with this increase in complexity. To overcome these limitations application specific design solutions are more common. In this thesis we presents such solutions for real-time image processing. This work is part of the WITAS Unmanned Aerial Vehicle (UAV) project. Within this project we are developing a prototype UAV.<br/><br>
<br/><br>
We introduce Image Processing Data Flow Graph (IP-DFG), a data flow based computational model that is suitable for modelling complex image processing algorithms. We also present IPAPI, a run-time system based on IP-DFG. We use IPAPI for early evaluation of image processing algorithms for the vision subsystem of the WITAS UAV prototype. This is carried out via co-simulation of IPAPI with the other subsystems, such as the reasoning subsystem and helicopter control subsystem. We also show how IPAPI can be used as a framework to derive an optimised implementation for the on-board system.<br/><br>
<br/><br>
FPGAs can be used to accelerate the image processing operations. Time multiplexed FPGAs (TMFPGAs) have shown potential in both reducing the price of FPGAs and in hiding the reconfiguration time for dynamically reconfigured FPGAs. To use a TMFPGA, the operation must be temporally partitioned. We present an algorithm that does temporal<br/><br>
partitioning on a technology mapped net-list. This makes it possible to use excising design tools when developing for TMFPGAs.},
  author       = {Andersson, Per},
  language     = {eng},
  note         = {Licentiate Thesis},
  title        = {Modelling and Implementation of a vision system for embedded systems},
  year         = {2003},
}