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Accelerating vector operations by utilizing reconfigurable coprocessor architectures

Svensson, Henrik LU ; Lenart, Thomas LU and Öwall, Viktor LU (2007) 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 In [Host publication title missing] p.3972-3975
Abstract
To enhance performance of digital signal processing tasks while keeping the flexibility of programmable solutions is a clear motivation for coprocessors implemented as reconfigurable hardware blocks. This paper investigates the applicability of such coprocessors targeting digital signal processing multi-media applications, initially in the field of speech and audio. A tightly coupled coprocessor architecture with reconfigurable datapath and a local memory system is presented. The coprocessor interacts with the main processor through asynchronous FIFOs. Three computational models that provide support for functionality of different granularities to be accelerated are investigated. A speedup in the range of 2 to 46 compared to processor... (More)
To enhance performance of digital signal processing tasks while keeping the flexibility of programmable solutions is a clear motivation for coprocessors implemented as reconfigurable hardware blocks. This paper investigates the applicability of such coprocessors targeting digital signal processing multi-media applications, initially in the field of speech and audio. A tightly coupled coprocessor architecture with reconfigurable datapath and a local memory system is presented. The coprocessor interacts with the main processor through asynchronous FIFOs. Three computational models that provide support for functionality of different granularities to be accelerated are investigated. A speedup in the range of 2 to 46 compared to processor execution is achieved for vector operations and larger kernels such as autocorrelation, block filtering and Fast Fourier Transform. © 2007 IEEE. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
Coprocessors, Reconfigurable coprocessors, Programmable solutions
in
[Host publication title missing]
pages
3972 - 3975
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007
external identifiers
  • wos:000251608405080
  • other:CODEN: PICSDI
  • scopus:34548817861
ISSN
2158-1525
0271-4310
language
English
LU publication?
yes
id
320e92d3-4c8a-46b7-88f2-5bd834c85d28 (old id 643342)
date added to LUP
2007-12-04 11:09:42
date last changed
2017-06-04 03:37:40
@inproceedings{320e92d3-4c8a-46b7-88f2-5bd834c85d28,
  abstract     = {To enhance performance of digital signal processing tasks while keeping the flexibility of programmable solutions is a clear motivation for coprocessors implemented as reconfigurable hardware blocks. This paper investigates the applicability of such coprocessors targeting digital signal processing multi-media applications, initially in the field of speech and audio. A tightly coupled coprocessor architecture with reconfigurable datapath and a local memory system is presented. The coprocessor interacts with the main processor through asynchronous FIFOs. Three computational models that provide support for functionality of different granularities to be accelerated are investigated. A speedup in the range of 2 to 46 compared to processor execution is achieved for vector operations and larger kernels such as autocorrelation, block filtering and Fast Fourier Transform. © 2007 IEEE.},
  author       = {Svensson, Henrik and Lenart, Thomas and Öwall, Viktor},
  booktitle    = {[Host publication title missing]},
  issn         = {2158-1525},
  keyword      = {Coprocessors,Reconfigurable coprocessors,Programmable solutions},
  language     = {eng},
  pages        = {3972--3975},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {Accelerating vector operations by utilizing reconfigurable coprocessor architectures},
  year         = {2007},
}