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A 1070 pJ/b 169 Mb/s Quad-core Digital Baseband SoC for Distributed and Cooperative Massive MIMO in 28 nm FD-SOI

Prabhu, Hemanth LU ; Liu, Liang LU orcid ; Sheikh, Farhana and Edfors, Ove LU orcid (2021) 35th Symposium on VLSI Circuits, VLSI Circuits 2021 In IEEE Symposium on VLSI Circuits, Digest of Technical Papers 2021-June.
Abstract

A 2.2 mm2 full digital baseband SoC with four heterogeneous cores for 128-node 8-users distributed massive MIMO is presented. Two specialized DSPs perform rapid over-the-air synchronization within 0.1ms. A highly optimized 8-complex lane MIMO vector processor provides 4x hardware efficiency improvement over general-purpose processors. Circuit optimizations and the use of body-bias result in 1070 pJ/b measured energy at 169 Mb/s detection rate.

Please use this url to cite or link to this publication:
author
; ; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
host publication
2021 Symposium on VLSI Circuits, VLSI Circuits 2021
series title
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
volume
2021-June
article number
9492455
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
35th Symposium on VLSI Circuits, VLSI Circuits 2021
conference location
Virutal, Online
conference dates
2021-06-13 - 2021-06-19
external identifiers
  • scopus:85111839267
ISBN
9784863487796
DOI
10.23919/VLSICircuits52068.2021.9492455
language
English
LU publication?
yes
id
684f0a34-4c2c-41fe-8273-2f0a8c51ad00
date added to LUP
2022-03-18 16:07:27
date last changed
2024-03-21 06:24:38
@inproceedings{684f0a34-4c2c-41fe-8273-2f0a8c51ad00,
  abstract     = {{<p>A 2.2 mm2 full digital baseband SoC with four heterogeneous cores for 128-node 8-users distributed massive MIMO is presented. Two specialized DSPs perform rapid over-the-air synchronization within 0.1ms. A highly optimized 8-complex lane MIMO vector processor provides 4x hardware efficiency improvement over general-purpose processors. Circuit optimizations and the use of body-bias result in 1070 pJ/b measured energy at 169 Mb/s detection rate.</p>}},
  author       = {{Prabhu, Hemanth and Liu, Liang and Sheikh, Farhana and Edfors, Ove}},
  booktitle    = {{2021 Symposium on VLSI Circuits, VLSI Circuits 2021}},
  isbn         = {{9784863487796}},
  language     = {{eng}},
  month        = {{06}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  series       = {{IEEE Symposium on VLSI Circuits, Digest of Technical Papers}},
  title        = {{A 1070 pJ/b 169 Mb/s Quad-core Digital Baseband SoC for Distributed and Cooperative Massive MIMO in 28 nm FD-SOI}},
  url          = {{http://dx.doi.org/10.23919/VLSICircuits52068.2021.9492455}},
  doi          = {{10.23919/VLSICircuits52068.2021.9492455}},
  volume       = {{2021-June}},
  year         = {{2021}},
}