Complementary III-V heterojunction lateral NW Tunnel FET technology on Si
(2016) 36th IEEE Symposium on VLSI Technology, VLSI Technology 2016 2016-September.- Abstract
- We demonstrate for the first time a technology which allows the monolithic integration of both p-Type (InAs-Si) and n-Type (InAs-GaSb) heterojunction Tunnel FETs (TFET) laterally on a Si substrate. The lateral heterojunction nanowire (NW) structures are implemented using top-down CMOS-compatible processes combined with Template-Assisted Selective Epitaxy (TASE) [1] of the III-V materials. Sub-40nm InAs-Si p-TFETs and InAs-GaSb n-TFETs have been fabricated and represent to the best of our knowledge the first lateral III-V heterostructure NW TFETs. The InAs-Si p-TFETs show excellent performance with average subthreshold swing, SSave, of ∼70mV/dec. combined with an on-current, Ion, of 4μA/μm at VDS =... (More) 
- We demonstrate for the first time a technology which allows the monolithic integration of both p-Type (InAs-Si) and n-Type (InAs-GaSb) heterojunction Tunnel FETs (TFET) laterally on a Si substrate. The lateral heterojunction nanowire (NW) structures are implemented using top-down CMOS-compatible processes combined with Template-Assisted Selective Epitaxy (TASE) [1] of the III-V materials. Sub-40nm InAs-Si p-TFETs and InAs-GaSb n-TFETs have been fabricated and represent to the best of our knowledge the first lateral III-V heterostructure NW TFETs. The InAs-Si p-TFETs show excellent performance with average subthreshold swing, SSave, of ∼70mV/dec. combined with an on-current, Ion, of 4μA/μm at VDS = VGS =-0.5V. The InAs-GaSb n-TFETs have about an order of magnitude higher Ion, but SS is deteriorated due to high interface traps density (Dit). (Less)
- author
- 						Cutaia, Davide
	; 						Moselund, Kirsten E.
	; 						Schmid, Heinz
	; 						Borg, M.
				LU
				 ; 						Olziersky, Antonis
	 and 						Riel, Heike ; 						Olziersky, Antonis
	 and 						Riel, Heike
- organization
- publishing date
- 2016-09-21
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- 2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016
- volume
- 2016-September
- article number
- 7573444
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- 36th IEEE Symposium on VLSI Technology, VLSI Technology 2016
- conference location
- Honolulu, United States
- conference dates
- 2016-06-13 - 2016-06-16
- external identifiers
- 
                - scopus:84991011686
 
- ISBN
- 9781509006373
- DOI
- 10.1109/VLSIT.2016.7573444
- language
- English
- LU publication?
- no
- id
- 68a9f15c-533c-4b51-a307-3404ef1a71a0
- date added to LUP
- 2017-03-02 13:55:32
- date last changed
- 2025-10-14 12:55:01
@inproceedings{68a9f15c-533c-4b51-a307-3404ef1a71a0,
  abstract     = {{<p>We demonstrate for the first time a technology which allows the monolithic integration of both p-Type (InAs-Si) and n-Type (InAs-GaSb) heterojunction Tunnel FETs (TFET) laterally on a Si substrate. The lateral heterojunction nanowire (NW) structures are implemented using top-down CMOS-compatible processes combined with Template-Assisted Selective Epitaxy (TASE) [1] of the III-V materials. Sub-40nm InAs-Si p-TFETs and InAs-GaSb n-TFETs have been fabricated and represent to the best of our knowledge the first lateral III-V heterostructure NW TFETs. The InAs-Si p-TFETs show excellent performance with average subthreshold swing, SS<sub>ave</sub>, of ∼70mV/dec. combined with an on-current, I<sub>on</sub>, of 4μA/μm at V<sub>DS</sub> = V<sub>GS</sub> =-0.5V. The InAs-GaSb n-TFETs have about an order of magnitude higher I<sub>on</sub>, but SS is deteriorated due to high interface traps density (D<sub>it</sub>).</p>}},
  author       = {{Cutaia, Davide and Moselund, Kirsten E. and Schmid, Heinz and Borg, M. and Olziersky, Antonis and Riel, Heike}},
  booktitle    = {{2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016}},
  isbn         = {{9781509006373}},
  language     = {{eng}},
  month        = {{09}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  title        = {{Complementary III-V heterojunction lateral NW Tunnel FET technology on Si}},
  url          = {{http://dx.doi.org/10.1109/VLSIT.2016.7573444}},
  doi          = {{10.1109/VLSIT.2016.7573444}},
  volume       = {{2016-September}},
  year         = {{2016}},
}