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High-Density Standard Cell Library for Sequential 3D Integrated Circuits

Prieto, Arturo LU and Rodrigues, Joachim LU (2024) 32nd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2024
Abstract

Research efforts to push the integration density of circuits with technologies that transcend Moore's law have gained significant attention in recent years. This study investigates the silicon area gains of Sequential 3D technology, utilizing the third dimension of integrated circuits by accommodating nMOS and pMOS transistors in two stacked tiers with high-density and low-pitch 3D vias. The efficiency of the proposed integration strategy is exemplified through the design of a library with high-density 3D standard cells, including sequential and combinational logic. The integration of 3D vias within the standard cells mitigates the effort required for inter-tier connections during the routing of integrated circuits. Subsequent analysis... (More)

Research efforts to push the integration density of circuits with technologies that transcend Moore's law have gained significant attention in recent years. This study investigates the silicon area gains of Sequential 3D technology, utilizing the third dimension of integrated circuits by accommodating nMOS and pMOS transistors in two stacked tiers with high-density and low-pitch 3D vias. The efficiency of the proposed integration strategy is exemplified through the design of a library with high-density 3D standard cells, including sequential and combinational logic. The integration of 3D vias within the standard cells mitigates the effort required for inter-tier connections during the routing of integrated circuits. Subsequent analysis indicated an average silicon area reduction of 36 % in comparison to commercially available libraries with purely planar cells. The proposed 3D cells have been incorporated into a commercial design flow for a 28 nm process technology and have been benchmarked using examples of large-scale integration designs, indicating an area and wirelength reduction of 44 % and 23 %, respectively.

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Please use this url to cite or link to this publication:
author
and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
3D Cell, High-Density, Library, More-than-Moore, Partitioning, Sequential 3D
host publication
2024 IFIP/IEEE 32nd International Conference on Very Large Scale Integration, VLSI-SoC 2024
publisher
IEEE Computer Society
conference name
32nd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2024
conference location
Tanger, Morocco
conference dates
2024-10-06 - 2024-10-09
external identifiers
  • scopus:85213575798
ISBN
9798331539672
DOI
10.1109/VLSI-SoC62099.2024.10767816
language
English
LU publication?
yes
id
69948f83-5168-4052-84a5-59c2c9fa46b1
date added to LUP
2025-02-25 11:20:09
date last changed
2025-06-03 19:22:04
@inproceedings{69948f83-5168-4052-84a5-59c2c9fa46b1,
  abstract     = {{<p>Research efforts to push the integration density of circuits with technologies that transcend Moore's law have gained significant attention in recent years. This study investigates the silicon area gains of Sequential 3D technology, utilizing the third dimension of integrated circuits by accommodating nMOS and pMOS transistors in two stacked tiers with high-density and low-pitch 3D vias. The efficiency of the proposed integration strategy is exemplified through the design of a library with high-density 3D standard cells, including sequential and combinational logic. The integration of 3D vias within the standard cells mitigates the effort required for inter-tier connections during the routing of integrated circuits. Subsequent analysis indicated an average silicon area reduction of 36 % in comparison to commercially available libraries with purely planar cells. The proposed 3D cells have been incorporated into a commercial design flow for a 28 nm process technology and have been benchmarked using examples of large-scale integration designs, indicating an area and wirelength reduction of 44 % and 23 %, respectively.</p>}},
  author       = {{Prieto, Arturo and Rodrigues, Joachim}},
  booktitle    = {{2024 IFIP/IEEE 32nd International Conference on Very Large Scale Integration, VLSI-SoC 2024}},
  isbn         = {{9798331539672}},
  keywords     = {{3D Cell; High-Density; Library; More-than-Moore; Partitioning; Sequential 3D}},
  language     = {{eng}},
  publisher    = {{IEEE Computer Society}},
  title        = {{High-Density Standard Cell Library for Sequential 3D Integrated Circuits}},
  url          = {{http://dx.doi.org/10.1109/VLSI-SoC62099.2024.10767816}},
  doi          = {{10.1109/VLSI-SoC62099.2024.10767816}},
  year         = {{2024}},
}