A chip for linearization of RF power amplifiers using digital predistortion with a bit-parallel complex multiplier
(1999) 1. p.346-349- Abstract
- This paper presents a custom chip for linearization of RF power amplifiers using digital predistortion. The chip has been implemented in a standard digital 0.8 μm CMOS process with standard static cells and single-phase clocking. A systolic complex multiplier based on distributed arithmetic constitutes the core of the chip. The nonlinear function is realized with a look-up table containing complex gain factors applied to the complex multiplier. The maximum clock frequency was found by means of simulation to be 105 MHz corresponding to 21 Msamples/s throughput with 3 W power consumption using 5 V supply voltage. The fabricated chip is fully functional and has been measured up to 60 MHz clock frequency with 825 mW power consumption with 3.3... (More)
- This paper presents a custom chip for linearization of RF power amplifiers using digital predistortion. The chip has been implemented in a standard digital 0.8 μm CMOS process with standard static cells and single-phase clocking. A systolic complex multiplier based on distributed arithmetic constitutes the core of the chip. The nonlinear function is realized with a look-up table containing complex gain factors applied to the complex multiplier. The maximum clock frequency was found by means of simulation to be 105 MHz corresponding to 21 Msamples/s throughput with 3 W power consumption using 5 V supply voltage. The fabricated chip is fully functional and has been measured up to 60 MHz clock frequency with 825 mW power consumption with 3.3 V supply voltage. Operation at 1.5 V supply voltage allows 10 MHz clock frequency with 35 mW power consumption (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/1051522
- author
- Andreani, Pietro LU ; Sundström, Lars ; Karlsson, Niklas and Svensson, Mikael
- organization
- publishing date
- 1999
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, 1999. ISCAS '99.
- volume
- 1
- pages
- 346 - 349
- external identifiers
-
- scopus:0032692408
- ISBN
- 0-7803-5471-0
- DOI
- 10.1109/ISCAS.1999.777874
- language
- English
- LU publication?
- yes
- id
- 6fc7c4c1-0cd2-428a-ba4a-8ca343ca3ea3 (old id 1051522)
- alternative location
- http://ieeexplore.ieee.org/iel5/6311/16892/00777874.pdf
- date added to LUP
- 2016-04-04 14:39:17
- date last changed
- 2022-01-30 02:22:34
@inproceedings{6fc7c4c1-0cd2-428a-ba4a-8ca343ca3ea3,
abstract = {{This paper presents a custom chip for linearization of RF power amplifiers using digital predistortion. The chip has been implemented in a standard digital 0.8 μm CMOS process with standard static cells and single-phase clocking. A systolic complex multiplier based on distributed arithmetic constitutes the core of the chip. The nonlinear function is realized with a look-up table containing complex gain factors applied to the complex multiplier. The maximum clock frequency was found by means of simulation to be 105 MHz corresponding to 21 Msamples/s throughput with 3 W power consumption using 5 V supply voltage. The fabricated chip is fully functional and has been measured up to 60 MHz clock frequency with 825 mW power consumption with 3.3 V supply voltage. Operation at 1.5 V supply voltage allows 10 MHz clock frequency with 35 mW power consumption}},
author = {{Andreani, Pietro and Sundström, Lars and Karlsson, Niklas and Svensson, Mikael}},
booktitle = {{Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, 1999. ISCAS '99.}},
isbn = {{0-7803-5471-0}},
language = {{eng}},
pages = {{346--349}},
title = {{A chip for linearization of RF power amplifiers using digital predistortion with a bit-parallel complex multiplier}},
url = {{http://dx.doi.org/10.1109/ISCAS.1999.777874}},
doi = {{10.1109/ISCAS.1999.777874}},
volume = {{1}},
year = {{1999}},
}