HPVM2FPGA: Enabling True Hardware-Agnostic FPGA Programming
(2022) 33rd IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP 2022)- Abstract
- Current FPGA programming tools require extensive hardware-specific manual code tuning to achieve performance, which is intractable for most software application teams. We present HPVM2FPGA, a novel end-to-end compiler and autotuning system that can automatically tune hardware-agnostic programs for FPGAs. HPVM2FPGA uses a hardware-agnostic abstraction of parallelism as an intermediate representation (IR) to represent hardware-agnostic programs. HPVM2FPGA’s powerful optimization framework uses sophisticated compiler optimizations and design space exploration (DSE) to automatically tune a hardware-agnostic program for a given FPGA. HPVM2FPGA is able to support software programmers by shifting the burden of performing hardware-specific... (More)
- Current FPGA programming tools require extensive hardware-specific manual code tuning to achieve performance, which is intractable for most software application teams. We present HPVM2FPGA, a novel end-to-end compiler and autotuning system that can automatically tune hardware-agnostic programs for FPGAs. HPVM2FPGA uses a hardware-agnostic abstraction of parallelism as an intermediate representation (IR) to represent hardware-agnostic programs. HPVM2FPGA’s powerful optimization framework uses sophisticated compiler optimizations and design space exploration (DSE) to automatically tune a hardware-agnostic program for a given FPGA. HPVM2FPGA is able to support software programmers by shifting the burden of performing hardware-specific optimizations to the compiler and DSE. We show that HPVM2FPGA can achieve up to 33× speedup compared to unoptimized baselines and can match the performance of hand-tuned HLS code for three of four benchmarks. We have designed HPVM2FPGA to be a modular and extensible framework, and we expect it to match handtuned code for most programs as the system matures with more optimizations. Overall, we believe that it constitutes a solid step closer to fully hardware-agnostic FPGA programming, making it a suitable cornerstone for future FPGA compiler research. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/7030430e-acc6-433e-94de-43353be8e269
- author
- Ejjeh, Adel ; Medvinsky, Leon ; Councilman, Aaron ; Nehra, Hemang ; Sharma, Suraj ; Adve, Vikram ; Nardi, Luigi LU ; Nurvitadhi, Eriko and Rutenbar, Rob A
- organization
- publishing date
- 2022
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- IEEE 33rd International Conference on Application-specific Systems, Architectures and Processors (ASAP)
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- 33rd IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP 2022)
- conference location
- Gothenburg, Sweden
- conference dates
- 2022-07-12 - 2022-07-14
- external identifiers
-
- scopus:85132637604
- ISBN
- 978-1-6654-8308-7
- 978-1-6654-8309-4
- DOI
- 10.1109/ASAP54787.2022.00012
- language
- English
- LU publication?
- yes
- id
- 7030430e-acc6-433e-94de-43353be8e269
- alternative location
- https://ieeexplore.ieee.org/document/9912103
- http://publish.illinois.edu/hpvm-project/files/2022/07/22-ASAP-HPVM2FPGA.pdf
- date added to LUP
- 2022-09-16 18:14:17
- date last changed
- 2024-04-18 14:19:17
@inproceedings{7030430e-acc6-433e-94de-43353be8e269,
abstract = {{Current FPGA programming tools require extensive hardware-specific manual code tuning to achieve performance, which is intractable for most software application teams. We present HPVM2FPGA, a novel end-to-end compiler and autotuning system that can automatically tune hardware-agnostic programs for FPGAs. HPVM2FPGA uses a hardware-agnostic abstraction of parallelism as an intermediate representation (IR) to represent hardware-agnostic programs. HPVM2FPGA’s powerful optimization framework uses sophisticated compiler optimizations and design space exploration (DSE) to automatically tune a hardware-agnostic program for a given FPGA. HPVM2FPGA is able to support software programmers by shifting the burden of performing hardware-specific optimizations to the compiler and DSE. We show that HPVM2FPGA can achieve up to 33× speedup compared to unoptimized baselines and can match the performance of hand-tuned HLS code for three of four benchmarks. We have designed HPVM2FPGA to be a modular and extensible framework, and we expect it to match handtuned code for most programs as the system matures with more optimizations. Overall, we believe that it constitutes a solid step closer to fully hardware-agnostic FPGA programming, making it a suitable cornerstone for future FPGA compiler research.}},
author = {{Ejjeh, Adel and Medvinsky, Leon and Councilman, Aaron and Nehra, Hemang and Sharma, Suraj and Adve, Vikram and Nardi, Luigi and Nurvitadhi, Eriko and Rutenbar, Rob A}},
booktitle = {{IEEE 33rd International Conference on Application-specific Systems, Architectures and Processors (ASAP)}},
isbn = {{978-1-6654-8308-7}},
language = {{eng}},
publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
title = {{HPVM2FPGA: Enabling True Hardware-Agnostic FPGA Programming}},
url = {{http://dx.doi.org/10.1109/ASAP54787.2022.00012}},
doi = {{10.1109/ASAP54787.2022.00012}},
year = {{2022}},
}