On Time-Interleaving Errors in Beamforming Receivers
(2025) 20th International Conference on PhD Research in Microelectronics and Electronics, PRIME 2025- Abstract
Time-interleaved ADCs are a key building block in mm-wave receivers, where the use of multi-GHz signal bandwidths requires high-performance wide-band data conversion. It is therefore necessary to explore the beamforming receiver system impact of different time-interleaved ADC parameters and limitations, such as number of interleaved channels, mismatches between channels, non-idealities of the subADCs, and correlation between sub-ADCs. This paper presents a scalable testbench in MATLAB/Simulink which models time-interleaved pipeline ADCs with high fidelity. The testbench is used to investigate the impact of time-interleaving errors on digital, hybrid, and analog beamforming receivers, both with and without interfering signals. Results... (More)
Time-interleaved ADCs are a key building block in mm-wave receivers, where the use of multi-GHz signal bandwidths requires high-performance wide-band data conversion. It is therefore necessary to explore the beamforming receiver system impact of different time-interleaved ADC parameters and limitations, such as number of interleaved channels, mismatches between channels, non-idealities of the subADCs, and correlation between sub-ADCs. This paper presents a scalable testbench in MATLAB/Simulink which models time-interleaved pipeline ADCs with high fidelity. The testbench is used to investigate the impact of time-interleaving errors on digital, hybrid, and analog beamforming receivers, both with and without interfering signals. Results show that the combination of time-interleaving errors and interference causes a degradation in beamforming performance, even at relatively low SNDR levels. The effect is more pronounced in digital beamforming compared to hybrid and analog beamforming.
(Less)
- author
- Asli, Javad Bagheri
; Gannedahl, Rikard
LU
; Sjoland, Henrik
LU
and Alvandpour, Atila
- organization
- publishing date
- 2025
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- 6G, ADC, beamforming, phased array, pipeline, receiver, system-level test-bench, time-interleaving
- host publication
- 2025 20th International Conference on PhD Research in Microelectronics and Electronics, PRIME 2025
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- 20th International Conference on PhD Research in Microelectronics and Electronics, PRIME 2025
- conference location
- Taormina, Italy
- conference dates
- 2025-09-21 - 2025-09-24
- external identifiers
-
- scopus:105021610159
- ISBN
- 9798331503901
- DOI
- 10.1109/PRIME66228.2025.11203668
- language
- English
- LU publication?
- yes
- id
- 718cb011-9175-42f8-94a3-bc6d55cbc1b7
- date added to LUP
- 2026-02-10 15:27:45
- date last changed
- 2026-02-10 15:28:00
@inproceedings{718cb011-9175-42f8-94a3-bc6d55cbc1b7,
abstract = {{<p>Time-interleaved ADCs are a key building block in mm-wave receivers, where the use of multi-GHz signal bandwidths requires high-performance wide-band data conversion. It is therefore necessary to explore the beamforming receiver system impact of different time-interleaved ADC parameters and limitations, such as number of interleaved channels, mismatches between channels, non-idealities of the subADCs, and correlation between sub-ADCs. This paper presents a scalable testbench in MATLAB/Simulink which models time-interleaved pipeline ADCs with high fidelity. The testbench is used to investigate the impact of time-interleaving errors on digital, hybrid, and analog beamforming receivers, both with and without interfering signals. Results show that the combination of time-interleaving errors and interference causes a degradation in beamforming performance, even at relatively low SNDR levels. The effect is more pronounced in digital beamforming compared to hybrid and analog beamforming.</p>}},
author = {{Asli, Javad Bagheri and Gannedahl, Rikard and Sjoland, Henrik and Alvandpour, Atila}},
booktitle = {{2025 20th International Conference on PhD Research in Microelectronics and Electronics, PRIME 2025}},
isbn = {{9798331503901}},
keywords = {{6G; ADC; beamforming; phased array; pipeline; receiver; system-level test-bench; time-interleaving}},
language = {{eng}},
publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
title = {{On Time-Interleaving Errors in Beamforming Receivers}},
url = {{http://dx.doi.org/10.1109/PRIME66228.2025.11203668}},
doi = {{10.1109/PRIME66228.2025.11203668}},
year = {{2025}},
}