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A 28 GHz SiGe PLL for an 81-86 GHz E-band beam steering transmitter plus an I/Q phase imbalance detection and compensation circuit

Tired, Tobias LU ; Sjöland, Henrik LU ; Sandrup, Per; Wernehag, Johan LU ; ud Din, Imad and Törmänen, Markus LU (2015) In Analog Integrated Circuits and Signal Processing 84(3). p.383-398
Abstract
This paper presents two circuits, a complete 1.5 V 28 GHz SiGe beam steering PLL and a standalone 28 GHz QVCO with I/Q phase imbalance detection and compensation. The circuits were designed in a SiGe process with f T = 200 GHz. The PLL is intended to be used for beam steering in an 81–86 GHz E-band transmitter. Phase control is implemented by DC current injection at the output of a Gilbert architecture phase detector showing a simulated phase control sensitivity of 1.2°/µA over a range close to 180°. The simulations use layout parasitics for the QVCO, frequency divider, and phase detector, and an electromagnetic model for the QVCO inductors. The divider is implemented with four cascaded divide-by-two current-mode-logic blocks for a... (More)
This paper presents two circuits, a complete 1.5 V 28 GHz SiGe beam steering PLL and a standalone 28 GHz QVCO with I/Q phase imbalance detection and compensation. The circuits were designed in a SiGe process with f T = 200 GHz. The PLL is intended to be used for beam steering in an 81–86 GHz E-band transmitter. Phase control is implemented by DC current injection at the output of a Gilbert architecture phase detector showing a simulated phase control sensitivity of 1.2°/µA over a range close to 180°. The simulations use layout parasitics for the QVCO, frequency divider, and phase detector, and an electromagnetic model for the QVCO inductors. The divider is implemented with four cascaded divide-by-two current-mode-logic blocks for a reference frequency of 1.75 GHz. For closed loop simulations of PLL noise and stability, the QVCO is represented with a behavior model with added phase noise. This simulation technique enabled faster simulation time of the PLL. The PLL in band phase noise at 1 MHz offset equals −115 dBc/Hz. Excluding output buffers, the entire PLL consumes 52 mW plus a minimum 7 mW from a variable high voltage supply required to extend the PLL locking range. The measured phase noise of the standalone QVCO equals −100 dBc/Hz at 1 MHz offset. Since E-band radio links utilize higher order QAM modulation, the bit-error rate is sensitive to I/Q phase error. In the measured standalone QVCO with I/Q phase imbalance detection and compensation, the error is detected in two cross coupled active mixers that have an output DC level proportional to the phase error. The error can then be eliminated adjusting the bias of four varactors connected to the QVCO outputs. The current consumption of the chip equals 14 mA from a 1.5 V supply and 57 mA from a 2.5 V supply dedicated to the detector and 28 GHz output measurement buffers (Less)
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author
organization
publishing date
type
Contribution to journal
publication status
published
subject
in
Analog Integrated Circuits and Signal Processing
volume
84
issue
3
pages
383 - 398
publisher
Springer
external identifiers
  • wos:000359013100006
  • scopus:84938741677
ISSN
0925-1030
DOI
10.1007/s10470-015-0594-z
language
English
LU publication?
yes
id
89cf24f8-fe79-44ae-a973-3c6420fd9d16 (old id 7458205)
date added to LUP
2015-07-20 10:12:06
date last changed
2017-08-27 04:52:57
@article{89cf24f8-fe79-44ae-a973-3c6420fd9d16,
  abstract     = {This paper presents two circuits, a complete 1.5 V 28 GHz SiGe beam steering PLL and a standalone 28 GHz QVCO with I/Q phase imbalance detection and compensation. The circuits were designed in a SiGe process with f T = 200 GHz. The PLL is intended to be used for beam steering in an 81–86 GHz E-band transmitter. Phase control is implemented by DC current injection at the output of a Gilbert architecture phase detector showing a simulated phase control sensitivity of 1.2°/µA over a range close to 180°. The simulations use layout parasitics for the QVCO, frequency divider, and phase detector, and an electromagnetic model for the QVCO inductors. The divider is implemented with four cascaded divide-by-two current-mode-logic blocks for a reference frequency of 1.75 GHz. For closed loop simulations of PLL noise and stability, the QVCO is represented with a behavior model with added phase noise. This simulation technique enabled faster simulation time of the PLL. The PLL in band phase noise at 1 MHz offset equals −115 dBc/Hz. Excluding output buffers, the entire PLL consumes 52 mW plus a minimum 7 mW from a variable high voltage supply required to extend the PLL locking range. The measured phase noise of the standalone QVCO equals −100 dBc/Hz at 1 MHz offset. Since E-band radio links utilize higher order QAM modulation, the bit-error rate is sensitive to I/Q phase error. In the measured standalone QVCO with I/Q phase imbalance detection and compensation, the error is detected in two cross coupled active mixers that have an output DC level proportional to the phase error. The error can then be eliminated adjusting the bias of four varactors connected to the QVCO outputs. The current consumption of the chip equals 14 mA from a 1.5 V supply and 57 mA from a 2.5 V supply dedicated to the detector and 28 GHz output measurement buffers},
  author       = {Tired, Tobias and Sjöland, Henrik and Sandrup, Per and Wernehag, Johan and ud Din, Imad and Törmänen, Markus},
  issn         = {0925-1030},
  language     = {eng},
  number       = {3},
  pages        = {383--398},
  publisher    = {Springer},
  series       = {Analog Integrated Circuits and Signal Processing},
  title        = {A 28 GHz SiGe PLL for an 81-86 GHz E-band beam steering transmitter plus an I/Q phase imbalance detection and compensation circuit},
  url          = {http://dx.doi.org/10.1007/s10470-015-0594-z},
  volume       = {84},
  year         = {2015},
}