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InAs Nanowire Devices and Circuits

Jansson, Kristofer LU (2015) In Series of licentiate and doctoral theses 2015.
Abstract (Swedish)
Popular Abstract in Swedish

Sedan introduktionen av transistorn och den integrerade kretsen har teknologin inom halvledarindustrin utvecklats i en mycket hög takt. Genom att bygga allt mindre och snabbare transistorer har en exponentiell förbättring av prestanda bibehållits sedan 1960-talet, ett fenomen känt som Moores Lag. Fram tills nyligen har utvecklingen mot högre prestanda och fler transistorer per chip framförallt drivits genom att minska storleken på transistorerna. I dagsläget är det inte ovanligt med miljardtals transistorer per chip och varje transistor är i storleksordningen av tiotals nanometer, motsvarande ett par hundra atomer eller en tiotusendel av tjockleken av ett hårstrå.



Närmast... (More)
Popular Abstract in Swedish

Sedan introduktionen av transistorn och den integrerade kretsen har teknologin inom halvledarindustrin utvecklats i en mycket hög takt. Genom att bygga allt mindre och snabbare transistorer har en exponentiell förbättring av prestanda bibehållits sedan 1960-talet, ett fenomen känt som Moores Lag. Fram tills nyligen har utvecklingen mot högre prestanda och fler transistorer per chip framförallt drivits genom att minska storleken på transistorerna. I dagsläget är det inte ovanligt med miljardtals transistorer per chip och varje transistor är i storleksordningen av tiotals nanometer, motsvarande ett par hundra atomer eller en tiotusendel av tjockleken av ett hårstrå.



Närmast totalt dominerande inom industrin är att bygga transistorer av halvledarmaterialet kisel. En halvledare är ett material som vanligtvis är en ganska dålig ledare, men vars ledningsförmåga relativt enkelt kan regleras. Detta fenomen används i en transistor som enkelt kan beskrivas som ett spänningsstyrt motstånd. Transistorer kan användas exempelvis för att förstärka elektriska signaler eller till att bygga logiska grindar, som kan användas för beräkningar i datorer.



Att bygga transistorer med hjälp av nanotrådar introducerar en mängd fördelar jämfört med traditionell transistorteknologi. Istället för kisel används indiumarsenid (InAs) som är ett halvledarmaterial som tillåter mycket högre elektronhastigheter än kisel, vilket innebär en förbättrad prestanda. Till skillnad från tradionell transistorteknologi som är orienterad i ett plan, står nanotrådstransistorerna upp i en 3D-struktur och tillverkas nedifrån och upp, lager för lager. Detta innebär att den tillgängliga ytan kan användas mer effektivt. Eftersom trådarna är helt omslutna med kontakter kan strömflödet kontrolleras mer effektivt, vilket är en förbättring jämfört med planära transistor. Tillsammans förväntas dessa innovationer uppnå en prestanda i terahertz-området.



I detta arbete presenteras simuleringar av nanotrådstransistorer där strukturen för transistorn optimeras och den förväntade prestandan uppskattas. Prestandan jämförs med konkurrerande teknologier och undersöks även från ett kretsperspektiv. (Less)
Abstract
Since the introduction of the transistor and the integrated circuit, the semiconductor industry has developed at a remarkable pace. By continuously fabricating smaller and faster transistors, it has been possible to maintain an exponential increase in performance, a phenomenon famously described by Moore’s Law. Today, billions of transistors are integrated on a single chip and the size of a transistor is on the scale of tens of nanometres. Until recently, the improvements in performance and integration density have been mostly driven by scaling down the transistor size. However, as the length scale is rapidly approaching that of only a few atoms, this scaling paradigm may not continue forever. Instead, the research community, as well as... (More)
Since the introduction of the transistor and the integrated circuit, the semiconductor industry has developed at a remarkable pace. By continuously fabricating smaller and faster transistors, it has been possible to maintain an exponential increase in performance, a phenomenon famously described by Moore’s Law. Today, billions of transistors are integrated on a single chip and the size of a transistor is on the scale of tens of nanometres. Until recently, the improvements in performance and integration density have been mostly driven by scaling down the transistor size. However, as the length scale is rapidly approaching that of only a few atoms, this scaling paradigm may not continue forever. Instead, the research community, as well as the industry, is investigating alternative structures and materials in order to further increase the performance.



One emerging technology for use in future electronic circuits is transistors based on nanowires. The nanowire transistor structure investigated in this work combines a number of key technologies to achieve a higher performance than traditional Si-based transistors. Epitaxially grown nanowires are naturally oriented in the vertical direction, which means that the devices may be fabricated from the bottom and up. This three-dimensional structure allows a higher integration density and enables the gate to completely surround the channel in a gate-all-around configuration. Combined with a high-k dielectric, this results in an excellent electrostatic gate control. Furthermore, nanowires have the unique ability to combine semiconductor materials with significantly different lattice constants. By introducing InAs as a channel material, a much higher electron mobility than for Si is achieved.



In this work, simulations of nanowire-based devices are performed and the ultimate performance is predicted. A nanowire transistor architecture with a realistic footprint is proposed and a roadmap is established for the scaling of the device structure, based on a set of technology nodes. Benchmarking is performed against competing technologies, both from a device and circuit perspective. The physical properties of nanowire transistors, and the corresponding capacitor structure, are investigated by band-structure simulations. Based on these simulations, a ballistic transport model is used to derive the intrinsic transistor characteristics. This is combined with an extensive evaluation and optimization of the parasitic elements in the transistor structure for each technology node.



It is demonstrated that an optimized nanowire transistor has the potential to operate at terahertz frequencies, while maintaining a low power consumption. A high quality factor and extremely high integration density is predicted for the nanowire capacitor structure. It is concluded that InAs nanowire devices show great potential for use in future electronic circuits, both in digital and analogue applications. (Less)
Please use this url to cite or link to this publication:
author
supervisor
opponent
  • Dr. Manhas, Sanjeev, Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, India
organization
publishing date
type
Thesis
publication status
published
subject
keywords
Modelling, Circuit, Simulation, Ballistic, Capacitor, Transistor, RF, Band structure, III-V semiconductor, InAs, MOSFET, Metal-oxide-semiconductor field-effect transistor, Nanowire, Amplifier
in
Series of licentiate and doctoral theses
volume
2015
pages
178 pages
publisher
Electrical and Information Technology, Lund University
defense location
Lecture hall E:1406, E-Building, Department of Electrical and Information Technology, Ole Römers väg 3, Lund University Faculty of Engineering, Lund
defense date
2015-09-11 10:15
ISSN
1654-790X
ISBN
978-91-7623-384-9
project
EIT_WWW Wireless with Wires
language
English
LU publication?
yes
id
3b3f98a8-e0c1-476e-8b27-be3ab405eb78 (old id 7760959)
date added to LUP
2015-08-19 08:50:26
date last changed
2016-09-19 08:44:49
@phdthesis{3b3f98a8-e0c1-476e-8b27-be3ab405eb78,
  abstract     = {Since the introduction of the transistor and the integrated circuit, the semiconductor industry has developed at a remarkable pace. By continuously fabricating smaller and faster transistors, it has been possible to maintain an exponential increase in performance, a phenomenon famously described by Moore’s Law. Today, billions of transistors are integrated on a single chip and the size of a transistor is on the scale of tens of nanometres. Until recently, the improvements in performance and integration density have been mostly driven by scaling down the transistor size. However, as the length scale is rapidly approaching that of only a few atoms, this scaling paradigm may not continue forever. Instead, the research community, as well as the industry, is investigating alternative structures and materials in order to further increase the performance.<br/><br>
<br/><br>
One emerging technology for use in future electronic circuits is transistors based on nanowires. The nanowire transistor structure investigated in this work combines a number of key technologies to achieve a higher performance than traditional Si-based transistors. Epitaxially grown nanowires are naturally oriented in the vertical direction, which means that the devices may be fabricated from the bottom and up. This three-dimensional structure allows a higher integration density and enables the gate to completely surround the channel in a gate-all-around configuration. Combined with a high-k dielectric, this results in an excellent electrostatic gate control. Furthermore, nanowires have the unique ability to combine semiconductor materials with significantly different lattice constants. By introducing InAs as a channel material, a much higher electron mobility than for Si is achieved.<br/><br>
<br/><br>
In this work, simulations of nanowire-based devices are performed and the ultimate performance is predicted. A nanowire transistor architecture with a realistic footprint is proposed and a roadmap is established for the scaling of the device structure, based on a set of technology nodes. Benchmarking is performed against competing technologies, both from a device and circuit perspective. The physical properties of nanowire transistors, and the corresponding capacitor structure, are investigated by band-structure simulations. Based on these simulations, a ballistic transport model is used to derive the intrinsic transistor characteristics. This is combined with an extensive evaluation and optimization of the parasitic elements in the transistor structure for each technology node. <br/><br>
<br/><br>
It is demonstrated that an optimized nanowire transistor has the potential to operate at terahertz frequencies, while maintaining a low power consumption. A high quality factor and extremely high integration density is predicted for the nanowire capacitor structure. It is concluded that InAs nanowire devices show great potential for use in future electronic circuits, both in digital and analogue applications.},
  author       = {Jansson, Kristofer},
  isbn         = {978-91-7623-384-9},
  issn         = {1654-790X},
  keyword      = {Modelling,Circuit,Simulation,Ballistic,Capacitor,Transistor,RF,Band structure,III-V semiconductor,InAs,MOSFET,Metal-oxide-semiconductor field-effect transistor,Nanowire,Amplifier},
  language     = {eng},
  pages        = {178},
  publisher    = {Electrical and Information Technology, Lund University},
  school       = {Lund University},
  series       = {Series of licentiate and doctoral theses},
  title        = {InAs Nanowire Devices and Circuits},
  volume       = {2015},
  year         = {2015},
}