A 10-bit Split-Capacitor SAR ADC with DAC Imbalance Estimation and Calibration
(2020) 2020 IEEE International Symposium on Circuits and Systems (ISCAS)- Abstract
- This paper presents a 10-bit SAR ADC with a sampling rate of 200 MS/s. To reduce area and power consumption, the ADC adopts a split-capacitor DAC, where the gain error is estimated and subsequently removed by means of a PRBS signal injected into the DAC and detected at the ADC output. The ADC has been designed and fabricated in a 22nm FD-SOI CMOS process, and achieves an SNDR of 48.7 dB and an SFDR of 66.7 dB for input frequencies up to the sampling frequency, with a power consumption of 4.3mW and an FoM of 152 dB.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/7b427bd9-6e0b-4299-809a-86ad7c2f68ab
- author
- Tan, Siyu LU ; Mastantuono, Daniele ; Strandberg, Roland ; Sundström, Lars ; Andreani, Piero LU and Palm, Mattias
- organization
- publishing date
- 2020
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- 2020 IEEE International Symposium on Circuits and Systems (ISCAS)
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- 2020 IEEE International Symposium on Circuits and Systems (ISCAS)
- conference location
- Sevilla, Spain
- conference dates
- 2020-10-10 - 2020-10-21
- external identifiers
-
- scopus:85109274135
- ISBN
- 978-1-7281-3320-1
- 978-1-7281-3321-8
- DOI
- 10.1109/ISCAS45731.2020.9180539
- language
- English
- LU publication?
- yes
- id
- 7b427bd9-6e0b-4299-809a-86ad7c2f68ab
- date added to LUP
- 2020-11-24 10:50:41
- date last changed
- 2024-07-11 03:34:39
@inproceedings{7b427bd9-6e0b-4299-809a-86ad7c2f68ab, abstract = {{This paper presents a 10-bit SAR ADC with a sampling rate of 200 MS/s. To reduce area and power consumption, the ADC adopts a split-capacitor DAC, where the gain error is estimated and subsequently removed by means of a PRBS signal injected into the DAC and detected at the ADC output. The ADC has been designed and fabricated in a 22nm FD-SOI CMOS process, and achieves an SNDR of 48.7 dB and an SFDR of 66.7 dB for input frequencies up to the sampling frequency, with a power consumption of 4.3mW and an FoM of 152 dB.}}, author = {{Tan, Siyu and Mastantuono, Daniele and Strandberg, Roland and Sundström, Lars and Andreani, Piero and Palm, Mattias}}, booktitle = {{2020 IEEE International Symposium on Circuits and Systems (ISCAS)}}, isbn = {{978-1-7281-3320-1}}, language = {{eng}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{A 10-bit Split-Capacitor SAR ADC with DAC Imbalance Estimation and Calibration}}, url = {{http://dx.doi.org/10.1109/ISCAS45731.2020.9180539}}, doi = {{10.1109/ISCAS45731.2020.9180539}}, year = {{2020}}, }