A PLL based 12 GHz LO generator with digital phase control in 90 nm CMOS
(2011) In Analog Integrated Circuits and Signal Processing 67(3). p.309-318- Abstract
- A 12 GHz PLL with digital output phase control has been implemented in a 90 nm CMOS process. It is intended for LO signal generation in integrated phased array transceivers. Locally placed PLLs eliminate the need of long high frequency LO routing to each transceiver in a phased array circuit. Routing losses are thereby reduced and the design of integrated phased array transceivers becomes more modular. A chip was manufactured, featuring two separate fully integrated PLLs operating at 12 GHz, with a common 1.5 GHz reference. The chip, including pads, measures 1050 × 700 μm2. Each PLL consumes 15 mA from a 1.2 V supply, with a typical measured phase noise of −110 dBc/Hz at 1 MHz offset. The phase control range exceeds 360°.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/1837606
- author
- Axholt, Andreas LU and Sjöland, Henrik LU
- organization
- publishing date
- 2011
- type
- Contribution to journal
- publication status
- published
- subject
- in
- Analog Integrated Circuits and Signal Processing
- volume
- 67
- issue
- 3
- pages
- 309 - 318
- publisher
- Springer
- external identifiers
-
- wos:000290162700005
- scopus:79958854079
- ISSN
- 0925-1030
- DOI
- 10.1007/s10470-011-9619-4
- project
- EIT_HSWC:RFNano RF tranceivers and nano devices
- language
- English
- LU publication?
- yes
- id
- 81b0185b-1b91-42ef-90f4-0b46e8c150ec (old id 1837606)
- date added to LUP
- 2016-04-01 14:09:25
- date last changed
- 2024-01-09 23:38:06
@article{81b0185b-1b91-42ef-90f4-0b46e8c150ec, abstract = {{A 12 GHz PLL with digital output phase control has been implemented in a 90 nm CMOS process. It is intended for LO signal generation in integrated phased array transceivers. Locally placed PLLs eliminate the need of long high frequency LO routing to each transceiver in a phased array circuit. Routing losses are thereby reduced and the design of integrated phased array transceivers becomes more modular. A chip was manufactured, featuring two separate fully integrated PLLs operating at 12 GHz, with a common 1.5 GHz reference. The chip, including pads, measures 1050 × 700 μm2. Each PLL consumes 15 mA from a 1.2 V supply, with a typical measured phase noise of −110 dBc/Hz at 1 MHz offset. The phase control range exceeds 360°.}}, author = {{Axholt, Andreas and Sjöland, Henrik}}, issn = {{0925-1030}}, language = {{eng}}, number = {{3}}, pages = {{309--318}}, publisher = {{Springer}}, series = {{Analog Integrated Circuits and Signal Processing}}, title = {{A PLL based 12 GHz LO generator with digital phase control in 90 nm CMOS}}, url = {{http://dx.doi.org/10.1007/s10470-011-9619-4}}, doi = {{10.1007/s10470-011-9619-4}}, volume = {{67}}, year = {{2011}}, }