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An Analog (7,5) Convolutional Decoder in 65 nm CMOS for Low Power Wireless Applications

Meraji, Reza LU ; Anderson, John B LU ; Sjöland, Henrik LU and Öwall, Viktor LU (2011) IEEE International Symposium on Circuits and Systems (ISCAS 2011), 2011 p.2881-2884
Abstract
A complete architecture with transistor level simulation is

presented for a low power analog convolutional decoder in 65 nm CMOS.

The decoder core operates in the weak inversion (sub-VT) and realizes the

BCJR decoding algorithm corresponding to the 4-state tail-biting trellis of

a (7,5) convolutional code. The complete decoder also incorporates serial

I/O digital interfaces and current mode differential DACs. The simulated

bit error rate is presented to illustrate the coding gain compared to an

uncoded system. Our results show that a low power, high throughput

convolutional decoder up to 1.25 Mb/s can be implemented using analog

circuitry with a total power... (More)
A complete architecture with transistor level simulation is

presented for a low power analog convolutional decoder in 65 nm CMOS.

The decoder core operates in the weak inversion (sub-VT) and realizes the

BCJR decoding algorithm corresponding to the 4-state tail-biting trellis of

a (7,5) convolutional code. The complete decoder also incorporates serial

I/O digital interfaces and current mode differential DACs. The simulated

bit error rate is presented to illustrate the coding gain compared to an

uncoded system. Our results show that a low power, high throughput

convolutional decoder up to 1.25 Mb/s can be implemented using analog

circuitry with a total power consumption of 84 μW. For low rate

applications the decoder consumes only 47 μW at a throughput of 250

kb/s. (Less)
Please use this url to cite or link to this publication:
author
; ; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
host publication
[Host publication title missing]
pages
2881 - 2884
conference name
IEEE International Symposium on Circuits and Systems (ISCAS 2011), 2011
conference location
Rio de Janeiro, Brazil
conference dates
2011-05-15 - 2011-05-18
external identifiers
  • wos:000297265303065
  • scopus:79960881619
ISSN
2158-1525
0271-4310
ISBN
978-1-4244-9473-6
DOI
10.1109/ISCAS.2011.5938233
language
English
LU publication?
yes
id
8374d13d-ecb5-4d41-8ba8-de3d35264e7c (old id 1852797)
date added to LUP
2016-04-04 07:10:27
date last changed
2022-01-29 01:49:37
@inproceedings{8374d13d-ecb5-4d41-8ba8-de3d35264e7c,
  abstract     = {{A complete architecture with transistor level simulation is<br/><br>
presented for a low power analog convolutional decoder in 65 nm CMOS.<br/><br>
The decoder core operates in the weak inversion (sub-VT) and realizes the<br/><br>
BCJR decoding algorithm corresponding to the 4-state tail-biting trellis of<br/><br>
a (7,5) convolutional code. The complete decoder also incorporates serial<br/><br>
I/O digital interfaces and current mode differential DACs. The simulated<br/><br>
bit error rate is presented to illustrate the coding gain compared to an<br/><br>
uncoded system. Our results show that a low power, high throughput<br/><br>
convolutional decoder up to 1.25 Mb/s can be implemented using analog<br/><br>
circuitry with a total power consumption of 84 μW. For low rate<br/><br>
applications the decoder consumes only 47 μW at a throughput of 250<br/><br>
kb/s.}},
  author       = {{Meraji, Reza and Anderson, John B and Sjöland, Henrik and Öwall, Viktor}},
  booktitle    = {{[Host publication title missing]}},
  isbn         = {{978-1-4244-9473-6}},
  issn         = {{2158-1525}},
  language     = {{eng}},
  pages        = {{2881--2884}},
  title        = {{An Analog (7,5) Convolutional Decoder in 65 nm CMOS for Low Power Wireless Applications}},
  url          = {{http://dx.doi.org/10.1109/ISCAS.2011.5938233}},
  doi          = {{10.1109/ISCAS.2011.5938233}},
  year         = {{2011}},
}