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Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65nm CMOS

Andersson, Oskar LU ; Mohammadi, Babak LU ; Meinerzhagen, Pascal; Burg, Andreas and Rodrigues, Joachim LU (2016) In IEEE Transactions on Circuits and Systems Part 1: Regular Papers 63(6). p.806-817
Abstract
In this study, design considerations for ultra low voltage (ULV) standard-cell based memories (SCM) are presented. Trade-offs for area cost, leakage power, access time, and access energy are discussed and realized using different read logic styles, latch architecture designs, and process options. Furthermore, deployment of multiple threshold voltages (Vth) options in a single standard-cell/bitcell enables additional architectural choices. Silicon measurements from five memory designs, optimized at the transistor level in conjunction with gate-level optimizations, are considered to demonstrate the different trade-off corners. Measurements show that substituting the storage element in an SCM with a D-latch using transistor stacking and... (More)
In this study, design considerations for ultra low voltage (ULV) standard-cell based memories (SCM) are presented. Trade-offs for area cost, leakage power, access time, and access energy are discussed and realized using different read logic styles, latch architecture designs, and process options. Furthermore, deployment of multiple threshold voltages (Vth) options in a single standard-cell/bitcell enables additional architectural choices. Silicon measurements from five memory designs, optimized at the transistor level in conjunction with gate-level optimizations, are considered to demonstrate the different trade-off corners. Measurements show that substituting the storage element in an SCM with a D-latch using transistor stacking and channel length stretching results in lowest leakage power. Alternatively, a pass- transistor based latch as storage element reduces the area footprint at a cost of reduced access speed, which can be compensated by using a lower-Vth pass-transistor. However, relatively high speed (tens of MHz) in the near- to subthreshold (sub-Vth) region is achievable if general purpose transistors are used instead of low power transistors. A discussion is included to illustrate when to implement ULV memories using SCMs and when to choose sub-Vth SRAMs. The discussion shows that the border is between 4-6 kb, depending on the number of words and the wordlength configuration. (Less)
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organization
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type
Contribution to journal
publication status
published
subject
in
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
volume
63
issue
6
pages
806 - 817
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • scopus:84979248391
  • wos:000380128200007
ISSN
1549-8328
DOI
10.1109/TCSI.2016.2537931
language
English
LU publication?
yes
id
f0144493-53a5-4912-a409-4f431f79c27e (old id 8627630)
date added to LUP
2016-02-16 12:45:05
date last changed
2017-11-12 04:07:21
@article{f0144493-53a5-4912-a409-4f431f79c27e,
  abstract     = {In this study, design considerations for ultra low voltage (ULV) standard-cell based memories (SCM) are presented. Trade-offs for area cost, leakage power, access time, and access energy are discussed and realized using different read logic styles, latch architecture designs, and process options. Furthermore, deployment of multiple threshold voltages (Vth) options in a single standard-cell/bitcell enables additional architectural choices. Silicon measurements from five memory designs, optimized at the transistor level in conjunction with gate-level optimizations, are considered to demonstrate the different trade-off corners. Measurements show that substituting the storage element in an SCM with a D-latch using transistor stacking and channel length stretching results in lowest leakage power. Alternatively, a pass- transistor based latch as storage element reduces the area footprint at a cost of reduced access speed, which can be compensated by using a lower-Vth pass-transistor. However, relatively high speed (tens of MHz) in the near- to subthreshold (sub-Vth) region is achievable if general purpose transistors are used instead of low power transistors. A discussion is included to illustrate when to implement ULV memories using SCMs and when to choose sub-Vth SRAMs. The discussion shows that the border is between 4-6 kb, depending on the number of words and the wordlength configuration.},
  author       = {Andersson, Oskar and Mohammadi, Babak and Meinerzhagen, Pascal and Burg, Andreas and Rodrigues, Joachim},
  issn         = {1549-8328},
  language     = {eng},
  month        = {04},
  number       = {6},
  pages        = {806--817},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  series       = {IEEE Transactions on Circuits and Systems Part 1: Regular Papers},
  title        = {Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65nm CMOS},
  url          = {http://dx.doi.org/10.1109/TCSI.2016.2537931},
  volume       = {63},
  year         = {2016},
}