Design of RF Properties for Vertical Nanowire MOSFETs
(2011) In IEEE Transactions on Nanotechnology 10(4). p.668-673- Abstract
- The RF performance of vertical nanowire metal-oxide-semiconductor field-effect transistors in realistic layouts has been calculated. The parasitic capacitances have been evaluated using full 3-D finite-element method calculations, combined with self-consistent Schrodinger-Poisson calculations for the intrinsic gate capacitances. It is shown that a performance comparable to planar FETs can be achieved in the vertical geometry by scaling the nanowire diameter and the wire-to-wire separation.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/2091609
- author
- Lind, Erik LU and Wernersson, Lars-Erik LU
- organization
- publishing date
- 2011
- type
- Contribution to journal
- publication status
- published
- subject
- keywords
- Field-effect transistors, InAs, metal-oxide-semiconductor field-effect, transistor (MOSFET), modeling, nanowire, parasitic capacitance
- in
- IEEE Transactions on Nanotechnology
- volume
- 10
- issue
- 4
- pages
- 668 - 673
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- external identifiers
-
- wos:000292966400002
- scopus:78649995472
- ISSN
- 1536-125X
- DOI
- 10.1109/TNANO.2010.2064783
- language
- English
- LU publication?
- yes
- id
- 87a058c1-eeaf-4ffd-8309-31683e0baffe (old id 2091609)
- date added to LUP
- 2016-04-01 14:50:36
- date last changed
- 2024-08-01 13:39:07
@article{87a058c1-eeaf-4ffd-8309-31683e0baffe, abstract = {{The RF performance of vertical nanowire metal-oxide-semiconductor field-effect transistors in realistic layouts has been calculated. The parasitic capacitances have been evaluated using full 3-D finite-element method calculations, combined with self-consistent Schrodinger-Poisson calculations for the intrinsic gate capacitances. It is shown that a performance comparable to planar FETs can be achieved in the vertical geometry by scaling the nanowire diameter and the wire-to-wire separation.}}, author = {{Lind, Erik and Wernersson, Lars-Erik}}, issn = {{1536-125X}}, keywords = {{Field-effect transistors; InAs; metal-oxide-semiconductor field-effect; transistor (MOSFET); modeling; nanowire; parasitic capacitance}}, language = {{eng}}, number = {{4}}, pages = {{668--673}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, series = {{IEEE Transactions on Nanotechnology}}, title = {{Design of RF Properties for Vertical Nanowire MOSFETs}}, url = {{http://dx.doi.org/10.1109/TNANO.2010.2064783}}, doi = {{10.1109/TNANO.2010.2064783}}, volume = {{10}}, year = {{2011}}, }