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An ASIC Implementation for V-BLAST Detection in 0.35um CMOS

Guo, Zhan LU and Nilsson, Peter LU (2004) Fourth IEEE International Symposium on Signal Processing and Information Technology, ISSPIT p.95-98
Abstract
The V-BLAST system has been shown to be capable of exploiting the capacity advantage of multiple antenna systems. The square root algorithm for V-BLAST detection is attractive to hardware implementations due to low computational complexity and numerical stability. A low complexity VLSI architecture of the square root algorithm is presented in this paper. The proposed architecture is scalable for various configurations, and implemented in AMIS 0.35 /spl mu/m CMOS technology for a 4/spl times/4 QPSK V-BLAST system. When the received symbol packet length is larger than or equal to 100 bytes, the implemented chip can achieve a maximally possible detection throughput of 128/spl sim/160 Mb/s with a maximal clock frequency of 80 MHz.
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
host publication
Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology, 2004.
pages
95 - 98
conference name
Fourth IEEE International Symposium on Signal Processing and Information Technology, ISSPIT
conference location
Rome, Italy
conference dates
2004-12-18 - 2004-12-21
external identifiers
  • wos:000228482900023
ISBN
0-7803-8689-2
DOI
10.1109/ISSPIT.2004.1433696
language
English
LU publication?
yes
id
9982a949-b833-4493-b7cd-f63c587a47f9 (old id 602814)
date added to LUP
2007-11-29 12:55:22
date last changed
2018-11-21 21:19:04
@inproceedings{9982a949-b833-4493-b7cd-f63c587a47f9,
  abstract     = {The V-BLAST system has been shown to be capable of exploiting the capacity advantage of multiple antenna systems. The square root algorithm for V-BLAST detection is attractive to hardware implementations due to low computational complexity and numerical stability. A low complexity VLSI architecture of the square root algorithm is presented in this paper. The proposed architecture is scalable for various configurations, and implemented in AMIS 0.35 /spl mu/m CMOS technology for a 4/spl times/4 QPSK V-BLAST system. When the received symbol packet length is larger than or equal to 100 bytes, the implemented chip can achieve a maximally possible detection throughput of 128/spl sim/160 Mb/s with a maximal clock frequency of 80 MHz.},
  author       = {Guo, Zhan and Nilsson, Peter},
  isbn         = {0-7803-8689-2},
  language     = {eng},
  location     = {Rome, Italy},
  pages        = {95--98},
  title        = {An ASIC Implementation for V-BLAST Detection in 0.35um CMOS},
  url          = {http://dx.doi.org/10.1109/ISSPIT.2004.1433696},
  year         = {2004},
}