A Programmable 10b up-to-6MS/s SAR-ADC Featuring Constant-FoM with On-Chip Reference Voltage Buffers
(2006) p.500-503- Abstract
- A 10bit SAR-ADC implemented in a 1.2V 0.13mum CMOS with 1VppdiffFS, based on capacitive-charge redistribution can be programmed with Fs up-to-6MS/s, guaranteeing an ENOB>9b with a SFDR>74dB. The static INL and DNL are 0.6LSB and 0.55LSB, respectively. On-chip reference buffer have been added and their power consumption dominates, giving a FoMap1pJ/conv. Sharing these buffers with other blocks in SoC structure, reduces the ADC power consumption to 200muW and the FoMap0.1pJ/conv. This appears an attractive solution for embedded ADC
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/1051096
- author
- Borghetti, F. ; Nielsen, J. ; Ferragina, V. ; Malcovati, P. ; Andreani, Pietro LU and Baschirotto, A.
- publishing date
- 2006
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- Proceedings of the 32nd European Solid-State Circuits Conference, 2006. ESSCIRC 2006.
- pages
- 500 - 503
- external identifiers
-
- scopus:57849161976
- ISSN
- 1930-8833
- ISBN
- 1-4244-0303-0
- DOI
- 10.1109/ESSCIR.2006.307499
- language
- English
- LU publication?
- no
- id
- a3c6b455-c772-4070-8fbd-16ce2df517d2 (old id 1051096)
- alternative location
- http://ieeexplore.ieee.org/iel5/4099684/4099685/04099813.pdf?tp=&isnumber=4099685&arnumber=4099813&punumber=4099684
- date added to LUP
- 2016-04-04 09:24:26
- date last changed
- 2022-01-29 17:43:55
@inproceedings{a3c6b455-c772-4070-8fbd-16ce2df517d2, abstract = {{A 10bit SAR-ADC implemented in a 1.2V 0.13mum CMOS with 1VppdiffFS, based on capacitive-charge redistribution can be programmed with Fs up-to-6MS/s, guaranteeing an ENOB>9b with a SFDR>74dB. The static INL and DNL are 0.6LSB and 0.55LSB, respectively. On-chip reference buffer have been added and their power consumption dominates, giving a FoMap1pJ/conv. Sharing these buffers with other blocks in SoC structure, reduces the ADC power consumption to 200muW and the FoMap0.1pJ/conv. This appears an attractive solution for embedded ADC}}, author = {{Borghetti, F. and Nielsen, J. and Ferragina, V. and Malcovati, P. and Andreani, Pietro and Baschirotto, A.}}, booktitle = {{Proceedings of the 32nd European Solid-State Circuits Conference, 2006. ESSCIRC 2006.}}, isbn = {{1-4244-0303-0}}, issn = {{1930-8833}}, language = {{eng}}, pages = {{500--503}}, title = {{A Programmable 10b up-to-6MS/s SAR-ADC Featuring Constant-FoM with On-Chip Reference Voltage Buffers}}, url = {{http://dx.doi.org/10.1109/ESSCIR.2006.307499}}, doi = {{10.1109/ESSCIR.2006.307499}}, year = {{2006}}, }