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A 5 GHz CT ^Delta;Σ ADC with 250 MHz Signal Bandwidth in 28 nm-FDSOI CMOS

Tan, Siyu LU ; Sundstrom, Lars ; Palm, Mattias ; Mattisson, Sven LU and Andreani, Pietro LU (2019) 5th IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip, SoC 2019
Abstract

This paper presents a continuous-time ΔΣ ADC in a 28nm-FDSOI CMOS technology. The ADC is clocked at 5GHz with a signal bandwidth of 250 MHz, for an oversampling ratio (OSR) of only 10. The conversion from high-level model to circuit-level implementation requires multiple high-speed design methodologies and a careful layout. A 4th order loop filter is adopted to enhance quantization noise shaping in presence of a low OSR. The loop filter is built with inverter-based integrators, and the transistors are tuned by adjusting body-biasing voltages. The extra loop delay exceeds one clock cycle, requiring two additional feedback paths to restore the nominal noise transfer function. Furthermore, current-mode logic is used in the digital part to... (More)

This paper presents a continuous-time ΔΣ ADC in a 28nm-FDSOI CMOS technology. The ADC is clocked at 5GHz with a signal bandwidth of 250 MHz, for an oversampling ratio (OSR) of only 10. The conversion from high-level model to circuit-level implementation requires multiple high-speed design methodologies and a careful layout. A 4th order loop filter is adopted to enhance quantization noise shaping in presence of a low OSR. The loop filter is built with inverter-based integrators, and the transistors are tuned by adjusting body-biasing voltages. The extra loop delay exceeds one clock cycle, requiring two additional feedback paths to restore the nominal noise transfer function. Furthermore, current-mode logic is used in the digital part to improve the signal transition speed. The ΔΣ ADC has a simulated SNDR of 73.1 dB for a simulated power consumption of 232mW.

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Please use this url to cite or link to this publication:
author
; ; ; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
host publication
2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019 : NORCHIP and International Symposium of System-on-Chip, SoC 2019 - Proceedings - NORCHIP and International Symposium of System-on-Chip, SoC 2019 - Proceedings
editor
Nurmi, Jari ; Ellervee, Peeter ; Halonen, Kari and Roning, Juha
article number
8906969
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
5th IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip, SoC 2019
conference location
Helsinki, Finland
conference dates
2019-10-29 - 2019-10-30
external identifiers
  • scopus:85076021385
ISBN
978-1-7281-2770-5
9781728127699
DOI
10.1109/NORCHIP.2019.8906969
language
English
LU publication?
yes
id
a40d6250-be94-4715-9cf8-cbd60479cbaa
date added to LUP
2020-01-03 11:33:16
date last changed
2024-06-26 08:47:57
@inproceedings{a40d6250-be94-4715-9cf8-cbd60479cbaa,
  abstract     = {{<p>This paper presents a continuous-time ΔΣ ADC in a 28nm-FDSOI CMOS technology. The ADC is clocked at 5GHz with a signal bandwidth of 250 MHz, for an oversampling ratio (OSR) of only 10. The conversion from high-level model to circuit-level implementation requires multiple high-speed design methodologies and a careful layout. A 4th order loop filter is adopted to enhance quantization noise shaping in presence of a low OSR. The loop filter is built with inverter-based integrators, and the transistors are tuned by adjusting body-biasing voltages. The extra loop delay exceeds one clock cycle, requiring two additional feedback paths to restore the nominal noise transfer function. Furthermore, current-mode logic is used in the digital part to improve the signal transition speed. The ΔΣ ADC has a simulated SNDR of 73.1 dB for a simulated power consumption of 232mW.</p>}},
  author       = {{Tan, Siyu and Sundstrom, Lars and Palm, Mattias and Mattisson, Sven and Andreani, Pietro}},
  booktitle    = {{2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019 : NORCHIP and International Symposium of System-on-Chip, SoC 2019 - Proceedings}},
  editor       = {{Nurmi, Jari and Ellervee, Peeter and Halonen, Kari and Roning, Juha}},
  isbn         = {{978-1-7281-2770-5}},
  language     = {{eng}},
  month        = {{11}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  title        = {{A 5 GHz CT ^Delta;Σ ADC with 250 MHz Signal Bandwidth in 28 nm-FDSOI CMOS}},
  url          = {{http://dx.doi.org/10.1109/NORCHIP.2019.8906969}},
  doi          = {{10.1109/NORCHIP.2019.8906969}},
  year         = {{2019}},
}