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VLSI Implementation of a Soft-Output Signal Detector for Multi-Mode Adaptive MIMO Systems

Liu, Liang LU ; Löfgren, Johan LU ; Nilsson, Peter LU and Öwall, Viktor LU (2013) In IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21(12). p.2262-2273
Abstract
This paper presents a multimode soft-output multiple-input multiple-output (MIMO) signal detector that is efficient in hardware cost and energy consumption. The detector is capable of dealing with spatial-multiplexing (SM),break space-division-multiple-access (SDMA), and spatial-diversity (SD) signals of 4 ✕ 4 antenna and 64-QAM modulation. Implementation-friendly algorithms, which reuse most of the mathematical operations in these three MIMO modes, are proposed to provide accurate soft detection information, i.e., log-likelihood ratio, with much reduced complexity. A unified reconfigurable VLSI architecture has been developed to eliminate the implementation of multiple detector modules. In addition, several block level technologies, such... (More)
This paper presents a multimode soft-output multiple-input multiple-output (MIMO) signal detector that is efficient in hardware cost and energy consumption. The detector is capable of dealing with spatial-multiplexing (SM),break space-division-multiple-access (SDMA), and spatial-diversity (SD) signals of 4 ✕ 4 antenna and 64-QAM modulation. Implementation-friendly algorithms, which reuse most of the mathematical operations in these three MIMO modes, are proposed to provide accurate soft detection information, i.e., log-likelihood ratio, with much reduced complexity. A unified reconfigurable VLSI architecture has been developed to eliminate the implementation of multiple detector modules. In addition, several block level technologies, such as parallel metric update and fast bit-flipping, are adopted to enable a more efficient design. To evaluate the proposed techniques, we implemented the triple-mode MIMO detector in a 65-nm CMOS technology. The core area is 0.25 mm2 with 83.7 K gates. The maximum detecting throughput is 1 Gb/s at 167-MHz clock frequency and 1.2-V supply, which archives the data rate envisioned by the emerging long-term evolution advanced standard. Under frequency-selective channels, the detector consumes 59.3-, 10.5-, and 169.6-pJ energy per bit detection in SM, SD, and SDMA modes, respectively. (Less)
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author
organization
publishing date
type
Contribution to journal
publication status
published
subject
in
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
volume
21
issue
12
pages
2262 - 2273
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • wos:000326107500009
  • scopus:84886539610
ISSN
1063-8210
DOI
10.1109/TVLSI.2012.2231706
language
English
LU publication?
yes
id
a93a9064-8483-4884-ae2e-47d6f2de9c9c (old id 3358069)
date added to LUP
2013-01-09 12:48:13
date last changed
2019-07-28 03:33:31
@article{a93a9064-8483-4884-ae2e-47d6f2de9c9c,
  abstract     = {This paper presents a multimode soft-output multiple-input multiple-output (MIMO) signal detector that is efficient in hardware cost and energy consumption. The detector is capable of dealing with spatial-multiplexing (SM),break space-division-multiple-access (SDMA), and spatial-diversity (SD) signals of 4 ✕ 4 antenna and 64-QAM modulation. Implementation-friendly algorithms, which reuse most of the mathematical operations in these three MIMO modes, are proposed to provide accurate soft detection information, i.e., log-likelihood ratio, with much reduced complexity. A unified reconfigurable VLSI architecture has been developed to eliminate the implementation of multiple detector modules. In addition, several block level technologies, such as parallel metric update and fast bit-flipping, are adopted to enable a more efficient design. To evaluate the proposed techniques, we implemented the triple-mode MIMO detector in a 65-nm CMOS technology. The core area is 0.25 mm2 with 83.7 K gates. The maximum detecting throughput is 1 Gb/s at 167-MHz clock frequency and 1.2-V supply, which archives the data rate envisioned by the emerging long-term evolution advanced standard. Under frequency-selective channels, the detector consumes 59.3-, 10.5-, and 169.6-pJ energy per bit detection in SM, SD, and SDMA modes, respectively.},
  author       = {Liu, Liang and Löfgren, Johan and Nilsson, Peter and Öwall, Viktor},
  issn         = {1063-8210},
  language     = {eng},
  number       = {12},
  pages        = {2262--2273},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  series       = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  title        = {VLSI Implementation of a Soft-Output Signal Detector for Multi-Mode Adaptive MIMO Systems},
  url          = {http://dx.doi.org/10.1109/TVLSI.2012.2231706},
  volume       = {21},
  year         = {2013},
}