Integrating Core Selection in the SOC Test Solution Design-Flow
Larsson, Erik LU
(2004)
International Test conference ITC04
p.1349-1358
- Abstract
- We propose a technique to integrate core selection in the SOC (system-on-chip) test solution design-flow. It can, in contrast to previous approaches, be used in the early design-space exploration phase (the core selection process) to evaluate the impact on the system's final test solution imposed by different design decisions, i.e. the core selection and the cores test characteristics. The proposed technique includes the interdependent problems: test scheduling, TAM (test access mechanism) design, test set selection and test resource floor-planning, and it minimizes a weighted cost function based on test time and TAM routing cost while considering test conflicts and test power limitations. An advantage with the technique is the novel... (More)
- We propose a technique to integrate core selection in the SOC (system-on-chip) test solution design-flow. It can, in contrast to previous approaches, be used in the early design-space exploration phase (the core selection process) to evaluate the impact on the system's final test solution imposed by different design decisions, i.e. the core selection and the cores test characteristics. The proposed technique includes the interdependent problems: test scheduling, TAM (test access mechanism) design, test set selection and test resource floor-planning, and it minimizes a weighted cost function based on test time and TAM routing cost while considering test conflicts and test power limitations. An advantage with the technique is the novel three-level power model: system, power-grid, and core. We have implemented and compared the proposed technique, a fast estimation technique and a computational extensive pseudo-exhaustive method, and the results demonstrate that our technique produces high quality solutions at reasonable computational cost. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/2341154
- author
- Larsson, Erik
LU
- publishing date
- 2004
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- testing, system-on-chip, test access mechanism, test scheduling, power optimization
- host publication
- [Host publication title missing]
- pages
- 1349 - 1358
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- International Test conference ITC04
- conference dates
- 0001-01-02
- external identifiers
-
- scopus:18144423550
- ISBN
- 0-7803-8580-2
- DOI
- 10.1109/TEST.2004.1387410
- language
- English
- LU publication?
- no
- id
- ad868065-06b8-467f-8d00-1dbc4855f5c0 (old id 2341154)
- date added to LUP
- 2016-04-04 10:12:07
- date last changed
- 2022-01-29 19:59:03
@inproceedings{ad868065-06b8-467f-8d00-1dbc4855f5c0,
abstract = {{We propose a technique to integrate core selection in the SOC (system-on-chip) test solution design-flow. It can, in contrast to previous approaches, be used in the early design-space exploration phase (the core selection process) to evaluate the impact on the system's final test solution imposed by different design decisions, i.e. the core selection and the cores test characteristics. The proposed technique includes the interdependent problems: test scheduling, TAM (test access mechanism) design, test set selection and test resource floor-planning, and it minimizes a weighted cost function based on test time and TAM routing cost while considering test conflicts and test power limitations. An advantage with the technique is the novel three-level power model: system, power-grid, and core. We have implemented and compared the proposed technique, a fast estimation technique and a computational extensive pseudo-exhaustive method, and the results demonstrate that our technique produces high quality solutions at reasonable computational cost.}},
author = {{Larsson, Erik}},
booktitle = {{[Host publication title missing]}},
isbn = {{0-7803-8580-2}},
keywords = {{testing; system-on-chip; test access mechanism; test scheduling; power optimization}},
language = {{eng}},
pages = {{1349--1358}},
publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
title = {{Integrating Core Selection in the SOC Test Solution Design-Flow}},
url = {{http://dx.doi.org/10.1109/TEST.2004.1387410}},
doi = {{10.1109/TEST.2004.1387410}},
year = {{2004}},
}