Test Planning for 3D Stacked ICs with Through-Silicon Vias
Sengupta, Breeta LU ; Ingelsson, Urban and Larsson, Erik LU
(2011)
Second IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/4305356
- author
- Sengupta, Breeta
LU
; Ingelsson, Urban
and Larsson, Erik
LU
- organization
- publishing date
- 2011
- type
- Contribution to conference
- publication status
- published
- subject
- conference name
- Second IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits
- conference location
- Anaheim, CA, United States
- conference dates
- 2011-09-22 - 2011-09-23
- language
- English
- LU publication?
- no
- id
- b4182574-5c1d-4231-9073-91bcf75fa5de (old id 4305356)
- date added to LUP
- 2016-04-04 14:18:42
- date last changed
- 2020-06-10 11:01:28
@misc{b4182574-5c1d-4231-9073-91bcf75fa5de,
author = {{Sengupta, Breeta and Ingelsson, Urban and Larsson, Erik}},
language = {{eng}},
title = {{Test Planning for 3D Stacked ICs with Through-Silicon Vias}},
url = {{https://lup.lub.lu.se/search/files/6330926/4857406.pdf}},
year = {{2011}},
}