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Buffer and Controller Minimization for Time-Constrained Testing of System-On-Chip

Larsson, Anders; Larsson, Erik LU ; Eles, Petru Ion and Peng, Zebo (2003) 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems DFT03 In [Host publication title missing] p.385-392
Abstract
Test scheduling and Test Access Mechanism (TAM)design are two important tasks in the development of a System-on-Chip (SOC)test solution.Previous test scheduling techniques assume a dedicated designed TAM which have the advantage of high exibility in the scheduling process. However,hardware verhead for implementing the TAM and additional routing is required of the TAMs.In this paper we propose a technique that makes use of the existing functional buses for the test data transportation inside the SOC.We have dealt with the test scheduling problem with this new assumption and developed a technique to minimize the test-controller and buffer size for a bus- based multi-core SOC.We have solved the problem by using a constraint logic pr gramming... (More)
Test scheduling and Test Access Mechanism (TAM)design are two important tasks in the development of a System-on-Chip (SOC)test solution.Previous test scheduling techniques assume a dedicated designed TAM which have the advantage of high exibility in the scheduling process. However,hardware verhead for implementing the TAM and additional routing is required of the TAMs.In this paper we propose a technique that makes use of the existing functional buses for the test data transportation inside the SOC.We have dealt with the test scheduling problem with this new assumption and developed a technique to minimize the test-controller and buffer size for a bus- based multi-core SOC.We have solved the problem by using a constraint logic pr gramming (CLP) technique and demonstrated the ef ciency of our approach by running experiments on benchmark designs. (Less)
Please use this url to cite or link to this publication:
author
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
test access mechanisms, TAM, system-on-chip, SOC, data transportation, constraint logic programming, test scheduling
in
[Host publication title missing]
pages
385 - 392
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems DFT03
ISSN
1550-5774
ISBN
0-7695-2042-1
DOI
10.1109/DFTVS.2003.1250135
language
English
LU publication?
no
id
be0eb48e-ae0f-4814-a299-eb1ed9fced9a (old id 2341138)
date added to LUP
2012-02-10 13:29:00
date last changed
2018-05-29 11:47:07
@inproceedings{be0eb48e-ae0f-4814-a299-eb1ed9fced9a,
  abstract     = {Test scheduling and Test Access Mechanism (TAM)design are two important tasks in the development of a System-on-Chip (SOC)test solution.Previous test scheduling techniques assume a dedicated designed TAM which have the advantage of high exibility in the scheduling process. However,hardware verhead for implementing the TAM and additional routing is required of the TAMs.In this paper we propose a technique that makes use of the existing functional buses for the test data transportation inside the SOC.We have dealt with the test scheduling problem with this new assumption and developed a technique to minimize the test-controller and buffer size for a bus- based multi-core SOC.We have solved the problem by using a constraint logic pr gramming (CLP) technique and demonstrated the ef ciency of our approach by running experiments on benchmark designs.},
  author       = {Larsson, Anders and Larsson, Erik and Eles, Petru Ion and Peng, Zebo},
  booktitle    = {[Host publication title missing]},
  isbn         = {0-7695-2042-1},
  issn         = {1550-5774},
  keyword      = {test access mechanisms,TAM,system-on-chip,SOC,data transportation,constraint logic programming,test scheduling},
  language     = {eng},
  pages        = {385--392},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {Buffer and Controller Minimization for Time-Constrained Testing of System-On-Chip},
  url          = {http://dx.doi.org/10.1109/DFTVS.2003.1250135},
  year         = {2003},
}