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Stacking of heterostructures and metallic elements for a submicron resonant tunneling transistor

Lind, Erik LU orcid ; Lindström, Peter LU ; Pietzonka, I. ; Seifert, Werner LU and Wernersson, Lars-Erik LU (2002) Proceedings of 7th International Conference on Nanometer-Scale Science and Technology and 21st European Conference on Surface Science (NANO-7/ECOSS-21)
Abstract
We have successfully embedded a metal gate in-between two resonant tunneling double barrier heterostructures (RTD), thus realizing a three dimensional resonant tunneling transistor. The gate is placed 30 nm above and 100 below the two RTD's, respectively. The asymmetric gate allows for a unique control of the current-voltage characteristics, not only controlling the peak current but also the peak voltage. We have modeled the transistor with Cadence, a standard simulation package for circuit simulations, achieving good agreement with experimental data
Please use this url to cite or link to this publication:
author
; ; ; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
circuit simulations, peak voltage, simulation package, stacking, peak current, heterostructures, metallic elements, submicron resonant tunneling transistor, metal gate, resonant tunneling double barrier heterostructures, three dimensional resonant tunneling transistor, current-voltage characteristics, asymmetric gate, 30 to 100 nm, W-GaAs
host publication
7th International Conference on Nanometer-Scale Science and Technology and 21st European Conference on Surface Science
pages
2 pages
publisher
Lund University
conference name
Proceedings of 7th International Conference on Nanometer-Scale Science and Technology and 21st European Conference on Surface Science (NANO-7/ECOSS-21)
conference location
Malmö, Sweden
conference dates
2002-06-24 - 2002-06-28
language
English
LU publication?
yes
id
be8ffa1c-d92a-48fe-9977-90250104b345 (old id 610805)
date added to LUP
2016-04-04 11:00:42
date last changed
2025-04-04 15:09:44
@inproceedings{be8ffa1c-d92a-48fe-9977-90250104b345,
  abstract     = {{We have successfully embedded a metal gate in-between two resonant tunneling double barrier heterostructures (RTD), thus realizing a three dimensional resonant tunneling transistor. The gate is placed 30 nm above and 100 below the two RTD's, respectively. The asymmetric gate allows for a unique control of the current-voltage characteristics, not only controlling the peak current but also the peak voltage. We have modeled the transistor with Cadence, a standard simulation package for circuit simulations, achieving good agreement with experimental data}},
  author       = {{Lind, Erik and Lindström, Peter and Pietzonka, I. and Seifert, Werner and Wernersson, Lars-Erik}},
  booktitle    = {{7th International Conference on Nanometer-Scale Science and Technology and 21st European Conference on Surface Science}},
  keywords     = {{circuit simulations; peak voltage; simulation package; stacking; peak current; heterostructures; metallic elements; submicron resonant tunneling transistor; metal gate; resonant tunneling double barrier heterostructures; three dimensional resonant tunneling transistor; current-voltage characteristics; asymmetric gate; 30 to 100 nm; W-GaAs}},
  language     = {{eng}},
  publisher    = {{Lund University}},
  title        = {{Stacking of heterostructures and metallic elements for a submicron resonant tunneling transistor}},
  year         = {{2002}},
}