Double-edge-triggered D-flip-flop for high speed CMOS circuits
(1991) In IEEE Journal of Solid-State Circuits 26(8). p.1168-1170- Abstract
- Two circuits are proposed for double edge-triggered D flip-flops (DETDFFs). A DETDFF responds to both edges of the clock pulse. As compared with positive or negative edge-triggered flip-flops, a DETDFF has advantages in terms of power dissipation and speed. Delay figures for these circuits are measured by simulation. It is shown that these circuits are faster and have lower transistor counts than previously reported circuits. It is shown that these flip-flops can be used at 320-400-MHz clock frequency in a 2-μm technology.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/1758987
- author
- Afgahi, Morteza and Yuan, Jiren LU
- publishing date
- 1991
- type
- Contribution to journal
- publication status
- published
- subject
- in
- IEEE Journal of Solid-State Circuits
- volume
- 26
- issue
- 8
- pages
- 1168 - 1170
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- external identifiers
-
- scopus:0026207089
- ISSN
- 0018-9200
- DOI
- 10.1109/4.90071
- language
- English
- LU publication?
- no
- id
- c8aa25ff-7ffc-4e52-ab2b-101a68a2ff78 (old id 1758987)
- date added to LUP
- 2016-04-04 09:31:08
- date last changed
- 2021-05-23 05:10:53
@article{c8aa25ff-7ffc-4e52-ab2b-101a68a2ff78, abstract = {{Two circuits are proposed for double edge-triggered D flip-flops (DETDFFs). A DETDFF responds to both edges of the clock pulse. As compared with positive or negative edge-triggered flip-flops, a DETDFF has advantages in terms of power dissipation and speed. Delay figures for these circuits are measured by simulation. It is shown that these circuits are faster and have lower transistor counts than previously reported circuits. It is shown that these flip-flops can be used at 320-400-MHz clock frequency in a 2-μm technology.}}, author = {{Afgahi, Morteza and Yuan, Jiren}}, issn = {{0018-9200}}, language = {{eng}}, number = {{8}}, pages = {{1168--1170}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, series = {{IEEE Journal of Solid-State Circuits}}, title = {{Double-edge-triggered D-flip-flop for high speed CMOS circuits}}, url = {{http://dx.doi.org/10.1109/4.90071}}, doi = {{10.1109/4.90071}}, volume = {{26}}, year = {{1991}}, }