Embedded Tutorial: Access to On-chip Instruments via Functional Ports
(2024) 2024 IEEE 25th Latin American Test Symposium (LATS) p.1-2- Abstract
- Semiconductor technology constantly advances, enabling integrated circuits (ICs) with increasingly numerous, faster, and smaller transistors. While this progress offers many benefits, it also presents new challenges, such as tighter margins, wear-outs, and process variations. To effectively tackle these challenges, the conventional approach of using external test instruments during manufacturing testing must be complemented with on-chip instruments. These on-chip instruments facilitate the detection of defects that emerge over the operational lifetime of the IC. Accessing on-chip instruments poses a challenge. We will discuss traditional test access method (IEEE Std. 1149.1 (JTAG)), reconfigurable scan networks (IEEE Std. 1687 (IJTAG)) and... (More)
- Semiconductor technology constantly advances, enabling integrated circuits (ICs) with increasingly numerous, faster, and smaller transistors. While this progress offers many benefits, it also presents new challenges, such as tighter margins, wear-outs, and process variations. To effectively tackle these challenges, the conventional approach of using external test instruments during manufacturing testing must be complemented with on-chip instruments. These on-chip instruments facilitate the detection of defects that emerge over the operational lifetime of the IC. Accessing on-chip instruments poses a challenge. We will discuss traditional test access method (IEEE Std. 1149.1 (JTAG)), reconfigurable scan networks (IEEE Std. 1687 (IJTAG)) and ongoing developments using functional ports to access test instruments (IEEE Std. P1687.1 and IEEE Std. P2654). (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/c8cbb706-7fd7-4989-8adb-5e24b16412c0
- author
- Larsson, Erik
LU
- organization
- publishing date
- 2024-04-09
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- 2024 IEEE 25th Latin American Test Symposium (LATS)
- pages
- 1 - 2
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- 2024 IEEE 25th Latin American Test Symposium (LATS)
- conference dates
- 2024-04-09 - 2024-04-12
- ISBN
- 979-8-3503-6555-9
- DOI
- 10.1109/LATS62223.2024.10534621
- language
- English
- LU publication?
- yes
- id
- c8cbb706-7fd7-4989-8adb-5e24b16412c0
- date added to LUP
- 2024-06-11 10:53:28
- date last changed
- 2024-06-11 12:47:42
@inproceedings{c8cbb706-7fd7-4989-8adb-5e24b16412c0, abstract = {{Semiconductor technology constantly advances, enabling integrated circuits (ICs) with increasingly numerous, faster, and smaller transistors. While this progress offers many benefits, it also presents new challenges, such as tighter margins, wear-outs, and process variations. To effectively tackle these challenges, the conventional approach of using external test instruments during manufacturing testing must be complemented with on-chip instruments. These on-chip instruments facilitate the detection of defects that emerge over the operational lifetime of the IC. Accessing on-chip instruments poses a challenge. We will discuss traditional test access method (IEEE Std. 1149.1 (JTAG)), reconfigurable scan networks (IEEE Std. 1687 (IJTAG)) and ongoing developments using functional ports to access test instruments (IEEE Std. P1687.1 and IEEE Std. P2654).}}, author = {{Larsson, Erik}}, booktitle = {{2024 IEEE 25th Latin American Test Symposium (LATS)}}, isbn = {{979-8-3503-6555-9}}, language = {{eng}}, month = {{04}}, pages = {{1--2}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{Embedded Tutorial: Access to On-chip Instruments via Functional Ports}}, url = {{http://dx.doi.org/10.1109/LATS62223.2024.10534621}}, doi = {{10.1109/LATS62223.2024.10534621}}, year = {{2024}}, }