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A 1095 pJ/b 219 Mb/s Application-specific Instruction-set Processor for Distributed Massive MIMO in 22FDX

Attari, Mohammad LU ; Sanchez, Jesus Rodriguez LU ; Edfors, Ove LU orcid and Liu, Liang LU orcid (2024) 50th IEEE European Solid-State Electronics Research Conference, ESSERC 2024 p.257-260
Abstract

Distributed massive multiple-input multiple-output (D-MIMO) has been identified as a promising technology to meet the service requirements of 6 G wireless networks and beyond. The coordination between a massive number of distributed antennas introduces stiff challenges and requires a substantial amount of computing resources that must be put together with careful algorithm-architecture codesign. The process places a premium on flexibility, and toward this end the current paper presents an application-specific instruction set processor (ASIP) utilizing single instruction multiple data (SIMD), allied with programmer-visible hardware accelerators and a specialized memory subsystem, and employed in distributed and scalable massive MIMO... (More)

Distributed massive multiple-input multiple-output (D-MIMO) has been identified as a promising technology to meet the service requirements of 6 G wireless networks and beyond. The coordination between a massive number of distributed antennas introduces stiff challenges and requires a substantial amount of computing resources that must be put together with careful algorithm-architecture codesign. The process places a premium on flexibility, and toward this end the current paper presents an application-specific instruction set processor (ASIP) utilizing single instruction multiple data (SIMD), allied with programmer-visible hardware accelerators and a specialized memory subsystem, and employed in distributed and scalable massive MIMO systems. The chip is fabricated using the GF22nm FDX technology.

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Please use this url to cite or link to this publication:
author
; ; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
baseband ASIP, Distributed massive MIMO, Golub-Kahan, matrix decomposition, RISC-V, SIMD, SVD accelerator, systolic array
host publication
ESSERC 2024 - Proceedings : 50th IEEE European Solid-State Electronics Research Conference - 50th IEEE European Solid-State Electronics Research Conference
pages
4 pages
publisher
IEEE Computer Society
conference name
50th IEEE European Solid-State Electronics Research Conference, ESSERC 2024
conference location
Bruges, Belgium
conference dates
2024-09-09 - 2024-09-12
external identifiers
  • scopus:85208440556
ISBN
9798350388138
DOI
10.1109/ESSERC62670.2024.10719451
language
English
LU publication?
yes
id
cae142c8-5d55-497a-9f81-29a0a97d9600
date added to LUP
2025-02-18 10:56:49
date last changed
2025-06-10 19:52:36
@inproceedings{cae142c8-5d55-497a-9f81-29a0a97d9600,
  abstract     = {{<p>Distributed massive multiple-input multiple-output (D-MIMO) has been identified as a promising technology to meet the service requirements of 6 G wireless networks and beyond. The coordination between a massive number of distributed antennas introduces stiff challenges and requires a substantial amount of computing resources that must be put together with careful algorithm-architecture codesign. The process places a premium on flexibility, and toward this end the current paper presents an application-specific instruction set processor (ASIP) utilizing single instruction multiple data (SIMD), allied with programmer-visible hardware accelerators and a specialized memory subsystem, and employed in distributed and scalable massive MIMO systems. The chip is fabricated using the GF22nm FDX technology.</p>}},
  author       = {{Attari, Mohammad and Sanchez, Jesus Rodriguez and Edfors, Ove and Liu, Liang}},
  booktitle    = {{ESSERC 2024 - Proceedings : 50th IEEE European Solid-State Electronics Research Conference}},
  isbn         = {{9798350388138}},
  keywords     = {{baseband ASIP; Distributed massive MIMO; Golub-Kahan; matrix decomposition; RISC-V; SIMD; SVD accelerator; systolic array}},
  language     = {{eng}},
  pages        = {{257--260}},
  publisher    = {{IEEE Computer Society}},
  title        = {{A 1095 pJ/b 219 Mb/s Application-specific Instruction-set Processor for Distributed Massive MIMO in 22FDX}},
  url          = {{http://dx.doi.org/10.1109/ESSERC62670.2024.10719451}},
  doi          = {{10.1109/ESSERC62670.2024.10719451}},
  year         = {{2024}},
}