Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption
Ingelsson, Urban ; Kumar Goel, Sandeep ; Larsson, Erik LU
and Marinissen, Erik Jan
(2015)
In IEEE Transactions on Computers
64(12).
p.3335-3347
- Abstract
- System-on-chips (SOCs) and 3D stacked ICs are often tested for manufacturing defects in a modular fashion, enabling us to record the module test pass probability. We use this pass probability to exploit the abort-on-fail feature of automatic test equipment (ATE) and hence reduce the expected test time in the context of single-site testing. We present a model for calculation of expected test time, for which the abortable test unit can be a module test, a test pattern or a clock cycle. Given an SOC, with test architecture consisting of module test wrappers and test access mechanisms (TAMs), and given module test pass probabilities, we schedule the tests on each TAM to minimize the expected test time. We describe four scheduling heuristics,... (More)
- System-on-chips (SOCs) and 3D stacked ICs are often tested for manufacturing defects in a modular fashion, enabling us to record the module test pass probability. We use this pass probability to exploit the abort-on-fail feature of automatic test equipment (ATE) and hence reduce the expected test time in the context of single-site testing. We present a model for calculation of expected test time, for which the abortable test unit can be a module test, a test pattern or a clock cycle. Given an SOC, with test architecture consisting of module test wrappers and test access mechanisms (TAMs), and given module test pass probabilities, we schedule the tests on each TAM to minimize the expected test time. We describe four scheduling heuristics, one without and three with preemption. Experimental results for the ITC’02 SOC Test Benchmarks show 3.5% and 20% reduction of expected test time in SOCs with 0.89 and 0.71 SOC test pass probability respectively, without modification of SOC or ATE. Further experiments show how accurate estimates for the module test pass probability or the distribution of pass probability over test patterns need to be to lead to effective test schedulng. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/5050124
- author
- Ingelsson, Urban
; Kumar Goel, Sandeep
; Larsson, Erik
LU
and Marinissen, Erik Jan
- organization
- publishing date
- 2015
- type
- Contribution to journal
- publication status
- published
- subject
- keywords
- System-on-Chip, stacked integrated circuit, manufacturing test, modular test, reject-oriented analysis, abort-on- fail, test scheduling, preemptive scheduling
- in
- IEEE Transactions on Computers
- volume
- 64
- issue
- 12
- pages
- 3335 - 3347
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- external identifiers
-
- wos:000364867200002
- scopus:84947104481
- ISSN
- 0018-9340
- DOI
- 10.1109/TC.2015.2409840
- language
- English
- LU publication?
- yes
- id
- d629ba23-fe5c-40ac-a9fd-ca74d2bf0618 (old id 5050124)
- date added to LUP
- 2016-04-01 13:44:28
- date last changed
- 2022-01-27 20:48:25
@article{d629ba23-fe5c-40ac-a9fd-ca74d2bf0618,
abstract = {{System-on-chips (SOCs) and 3D stacked ICs are often tested for manufacturing defects in a modular fashion, enabling us to record the module test pass probability. We use this pass probability to exploit the abort-on-fail feature of automatic test equipment (ATE) and hence reduce the expected test time in the context of single-site testing. We present a model for calculation of expected test time, for which the abortable test unit can be a module test, a test pattern or a clock cycle. Given an SOC, with test architecture consisting of module test wrappers and test access mechanisms (TAMs), and given module test pass probabilities, we schedule the tests on each TAM to minimize the expected test time. We describe four scheduling heuristics, one without and three with preemption. Experimental results for the ITC’02 SOC Test Benchmarks show 3.5% and 20% reduction of expected test time in SOCs with 0.89 and 0.71 SOC test pass probability respectively, without modification of SOC or ATE. Further experiments show how accurate estimates for the module test pass probability or the distribution of pass probability over test patterns need to be to lead to effective test schedulng.}},
author = {{Ingelsson, Urban and Kumar Goel, Sandeep and Larsson, Erik and Marinissen, Erik Jan}},
issn = {{0018-9340}},
keywords = {{System-on-Chip; stacked integrated circuit; manufacturing test; modular test; reject-oriented analysis; abort-on- fail; test scheduling; preemptive scheduling}},
language = {{eng}},
number = {{12}},
pages = {{3335--3347}},
publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
series = {{IEEE Transactions on Computers}},
title = {{Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption}},
url = {{http://dx.doi.org/10.1109/TC.2015.2409840}},
doi = {{10.1109/TC.2015.2409840}},
volume = {{64}},
year = {{2015}},
}