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Highly Efficient Class-C CMOS VCOs, Including a Comparison With Class-B VCOs

Fanori, Luca LU and Andreani, Pietro LU (2013) In IEEE Journal of Solid-State Circuits 48(7). p.1730-1740
Abstract
This paper presents two class-C CMOS VCOs with a dynamic bias of the core transistors, which maximizes the oscillation amplitude without compromising the robustness of the oscillation start-up, thereby breaking the most severe trade-off in the original class-C topology. An analysis of several different oscillators, starting with the common class-B architecture and arriving to the proposed class-C design, shows that the latter exhibits a figure-of-merit (FoM) that is closest to the ideal FoM allowed by the integration technology. The class-C VCOs have been implemented in a 90 nm CMOS process with a thick top metal layer. They are tunable between 3.4 GHz and 4.5 GHz, covering a tuning range of 28%. Drawing 5.5 mA from 1.2 V, the phase noise... (More)
This paper presents two class-C CMOS VCOs with a dynamic bias of the core transistors, which maximizes the oscillation amplitude without compromising the robustness of the oscillation start-up, thereby breaking the most severe trade-off in the original class-C topology. An analysis of several different oscillators, starting with the common class-B architecture and arriving to the proposed class-C design, shows that the latter exhibits a figure-of-merit (FoM) that is closest to the ideal FoM allowed by the integration technology. The class-C VCOs have been implemented in a 90 nm CMOS process with a thick top metal layer. They are tunable between 3.4 GHz and 4.5 GHz, covering a tuning range of 28%. Drawing 5.5 mA from 1.2 V, the phase noise is lower than -152 dBc/Hz at a 20 MHz offset from a 4 GHz carrier. The resulting FoM is 191 dBc/Hz, and varies less than 1 dB across the tuning range. (Less)
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author
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
Class-C, CMOS, dynamic-bias, low phase noise, start-up, VCO
in
IEEE Journal of Solid-State Circuits
volume
48
issue
7
pages
1730 - 1740
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • wos:000320938600019
  • scopus:84879990996
ISSN
0018-9200
DOI
10.1109/JSSC.2013.2253402
language
English
LU publication?
yes
id
db240fef-adfa-46a4-84be-2766d2af0cc8 (old id 3979665)
date added to LUP
2016-04-01 13:27:48
date last changed
2020-04-01 03:47:54
@article{db240fef-adfa-46a4-84be-2766d2af0cc8,
  abstract     = {This paper presents two class-C CMOS VCOs with a dynamic bias of the core transistors, which maximizes the oscillation amplitude without compromising the robustness of the oscillation start-up, thereby breaking the most severe trade-off in the original class-C topology. An analysis of several different oscillators, starting with the common class-B architecture and arriving to the proposed class-C design, shows that the latter exhibits a figure-of-merit (FoM) that is closest to the ideal FoM allowed by the integration technology. The class-C VCOs have been implemented in a 90 nm CMOS process with a thick top metal layer. They are tunable between 3.4 GHz and 4.5 GHz, covering a tuning range of 28%. Drawing 5.5 mA from 1.2 V, the phase noise is lower than -152 dBc/Hz at a 20 MHz offset from a 4 GHz carrier. The resulting FoM is 191 dBc/Hz, and varies less than 1 dB across the tuning range.},
  author       = {Fanori, Luca and Andreani, Pietro},
  issn         = {0018-9200},
  language     = {eng},
  number       = {7},
  pages        = {1730--1740},
  publisher    = {IEEE - Institute of Electrical and Electronics Engineers Inc.},
  series       = {IEEE Journal of Solid-State Circuits},
  title        = {Highly Efficient Class-C CMOS VCOs, Including a Comparison With Class-B VCOs},
  url          = {http://dx.doi.org/10.1109/JSSC.2013.2253402},
  doi          = {10.1109/JSSC.2013.2253402},
  volume       = {48},
  year         = {2013},
}