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Area-efficient configurable high-throughput signal detector supporting multiple MIMO modes

Liu, Liang LU orcid ; Löfgren, Johan LU and Nilsson, Peter LU (2012) In IEEE Transactions on Circuits and Systems Part 1: Regular Papers 59(9). p.2085-2096
Abstract
Abstract in Undetermined
This paper presents a low-complexity, highthroughput,
and configurable multiple-input multiple-output
(MIMO) signal detector design solution targeting the emerging
Long-Term-Evolution-Advanced (LTE-A) downlink. The detector
supports signal detection of multiple MIMO modes, which
are spatial-multiplexing (SM), spatial-diversity (SD), and spacedivision-multiple-access (SDMA). Area-efficiency is achieved by
algorithm and architecture co-design where low-complexity, nearmaximum-likelihood (ML) detection algorithms are proposed
for these three MIMO modes respectively while keeping in
mind that the operations can be reused among different modes.
A parallel multistage VLSI... (More)
Abstract in Undetermined
This paper presents a low-complexity, highthroughput,
and configurable multiple-input multiple-output
(MIMO) signal detector design solution targeting the emerging
Long-Term-Evolution-Advanced (LTE-A) downlink. The detector
supports signal detection of multiple MIMO modes, which
are spatial-multiplexing (SM), spatial-diversity (SD), and spacedivision-multiple-access (SDMA). Area-efficiency is achieved by
algorithm and architecture co-design where low-complexity, nearmaximum-likelihood (ML) detection algorithms are proposed
for these three MIMO modes respectively while keeping in
mind that the operations can be reused among different modes.
A parallel multistage VLSI architecture is accordingly developed
that achieves high detection throughput and run-time
reconfigurability without extra hardware overhead. To further
improve the implementation efficiency, the detector also adopts an
orthogonal-real-value-decomposition (ORVD) aided candidatesharing
technology for low-cost partial Euclidean distance calculation
and a distributed interference cancelation scheme for a
critical path delay reduction. The proposed multi-mode MIMO
detector has been implemented using a 65-nm CMOS technology
with a core area of 0.18 mm2 (the equivalent gate-count is 88.7K),
representing a 22% less hardware-resource use than the state
of art in the open literature. Operating at 1.2-V supply with
250-MHz clock, the detector achieves a 3Gb/s throughput when
configured to the 4x4 64-QAM spatial-multiplexing mode, which
is about 1.5 times over previous implementations. Moreover, the
normalized energy consumption of 44.1 pJ/b is shown to be the
most energy-efficient design compared with other works. (Less)
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; and
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
spatial-diversity (SD), spatial-multiplexing (SM), signal detector, Multiple-input multiple-output (MIMO), spacedivision-multiple-access (SDMA), configurable, very-large scale integration (VLSI).
in
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
volume
59
issue
9
pages
2085 - 2096
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • wos:000308109600024
  • scopus:84865700118
ISSN
1549-8328
language
English
LU publication?
yes
id
e3867557-e8a6-4f34-b465-549af94dad55 (old id 2276781)
date added to LUP
2016-04-04 07:38:26
date last changed
2025-10-14 09:48:45
@article{e3867557-e8a6-4f34-b465-549af94dad55,
  abstract     = {{Abstract in Undetermined<br/>This paper presents a low-complexity, highthroughput,<br/>and configurable multiple-input multiple-output<br/>(MIMO) signal detector design solution targeting the emerging<br/>Long-Term-Evolution-Advanced (LTE-A) downlink. The detector<br/>supports signal detection of multiple MIMO modes, which<br/>are spatial-multiplexing (SM), spatial-diversity (SD), and spacedivision-multiple-access (SDMA). Area-efficiency is achieved by<br/>algorithm and architecture co-design where low-complexity, nearmaximum-likelihood (ML) detection algorithms are proposed<br/>for these three MIMO modes respectively while keeping in<br/>mind that the operations can be reused among different modes.<br/>A parallel multistage VLSI architecture is accordingly developed<br/>that achieves high detection throughput and run-time<br/>reconfigurability without extra hardware overhead. To further<br/>improve the implementation efficiency, the detector also adopts an<br/>orthogonal-real-value-decomposition (ORVD) aided candidatesharing<br/>technology for low-cost partial Euclidean distance calculation<br/>and a distributed interference cancelation scheme for a<br/>critical path delay reduction. The proposed multi-mode MIMO<br/>detector has been implemented using a 65-nm CMOS technology<br/>with a core area of 0.18 mm2 (the equivalent gate-count is 88.7K),<br/>representing a 22% less hardware-resource use than the state<br/>of art in the open literature. Operating at 1.2-V supply with<br/>250-MHz clock, the detector achieves a 3Gb/s throughput when<br/>configured to the 4x4 64-QAM spatial-multiplexing mode, which<br/>is about 1.5 times over previous implementations. Moreover, the<br/>normalized energy consumption of 44.1 pJ/b is shown to be the<br/>most energy-efficient design compared with other works.}},
  author       = {{Liu, Liang and Löfgren, Johan and Nilsson, Peter}},
  issn         = {{1549-8328}},
  keywords     = {{spatial-diversity (SD); spatial-multiplexing (SM); signal detector; Multiple-input multiple-output (MIMO); spacedivision-multiple-access (SDMA); configurable; very-large scale integration (VLSI).}},
  language     = {{eng}},
  number       = {{9}},
  pages        = {{2085--2096}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  series       = {{IEEE Transactions on Circuits and Systems Part 1: Regular Papers}},
  title        = {{Area-efficient configurable high-throughput signal detector supporting multiple MIMO modes}},
  volume       = {{59}},
  year         = {{2012}},
}