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A 2.8-3.8-GHz Low-Spur DTC-Based DPLL With a Class-D DCO in 65-nm CMOS

Mahmoud, Ahmed LU ; Andreani, Pietro LU and Pepe, Federico LU (2017) In IEEE Microwave and Wireless Components Letters 27(11). p.1010-1012
Abstract

We present a digital phase-locked loop (DPLL) operating from 2.8 to 3.8 GHz with an on-chip 40-MHz reference crystal oscillator. The DPLL makes use of a class-D digitally controlled oscillator and a digital-to-time converter with a single-bit (bang-bang) phase detector. The DPLL displays an excellent behavior in terms of in-band fractional spurs, which are consistently below -65 dBc across the tuning range, thanks to a number of digital correction algorithms running in the background. The 65-nm CMOS DPLL consumes 18.2 mW for an in-band phase noise of -102 dBc/Hz at 100-kHz offset.

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author
; and
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
Bang-bang phase detector (BBPD), class-D, Detectors, digital phase-locked loop (DPLL), digital-to-time converter (DTC), digitally controlled oscillator (DCO), Frequency conversion, least mean square (LMS), Phase locked loops, Phase noise, phase noise, pre-distorter, Solid state circuits, spurs, time-to-digital converter (TDC)., Tuning
in
IEEE Microwave and Wireless Components Letters
volume
27
issue
11
pages
1010 - 1012
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • wos:000414697100020
  • scopus:85030779654
ISSN
1531-1309
DOI
10.1109/LMWC.2017.2750089
language
English
LU publication?
yes
id
e643c0ce-042e-46b3-b375-765f318bc145
date added to LUP
2017-10-18 08:19:42
date last changed
2025-03-19 09:48:00
@article{e643c0ce-042e-46b3-b375-765f318bc145,
  abstract     = {{<p>We present a digital phase-locked loop (DPLL) operating from 2.8 to 3.8 GHz with an on-chip 40-MHz reference crystal oscillator. The DPLL makes use of a class-D digitally controlled oscillator and a digital-to-time converter with a single-bit (bang-bang) phase detector. The DPLL displays an excellent behavior in terms of in-band fractional spurs, which are consistently below -65 dBc across the tuning range, thanks to a number of digital correction algorithms running in the background. The 65-nm CMOS DPLL consumes 18.2 mW for an in-band phase noise of -102 dBc/Hz at 100-kHz offset.</p>}},
  author       = {{Mahmoud, Ahmed and Andreani, Pietro and Pepe, Federico}},
  issn         = {{1531-1309}},
  keywords     = {{Bang-bang phase detector (BBPD); class-D; Detectors; digital phase-locked loop (DPLL); digital-to-time converter (DTC); digitally controlled oscillator (DCO); Frequency conversion; least mean square (LMS); Phase locked loops; Phase noise; phase noise; pre-distorter; Solid state circuits; spurs; time-to-digital converter (TDC).; Tuning}},
  language     = {{eng}},
  number       = {{11}},
  pages        = {{1010--1012}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  series       = {{IEEE Microwave and Wireless Components Letters}},
  title        = {{A 2.8-3.8-GHz Low-Spur DTC-Based DPLL With a Class-D DCO in 65-nm CMOS}},
  url          = {{http://dx.doi.org/10.1109/LMWC.2017.2750089}},
  doi          = {{10.1109/LMWC.2017.2750089}},
  volume       = {{27}},
  year         = {{2017}},
}