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Vertical III-V nanowire MOSFETs, TFETs, and CMOS-Gates on Si : Processing in 3D

Wernersson, Lars Erik LU (2016) 74th Annual Device Research Conference, DRC 2016 In 74th Annual Device Research Conference, DRC 2016 2016-August.
Abstract

III-V MOSFETs are candidates for extension of the scaling roadmap beyond 10 nm. In the vertical direction, the requirements on gate-length scaling is less stringent and vertical III-V nanowire FETs are thus attractive for high density and low-power applications. While growth in the vertical direction allows flexibility in heterostructure combination and eases the path for integration on Si substrates, the processing in the vertical direction is still regarded challenging. Processing on the length scale of a few tens of nanometers has nevertheless been demonstrated including processing of vertical nanowire transistors with a diameter of 10 nm. Besides logic applications, III-V MOSFETs hold promises in the area of millimeter-wave... (More)

III-V MOSFETs are candidates for extension of the scaling roadmap beyond 10 nm. In the vertical direction, the requirements on gate-length scaling is less stringent and vertical III-V nanowire FETs are thus attractive for high density and low-power applications. While growth in the vertical direction allows flexibility in heterostructure combination and eases the path for integration on Si substrates, the processing in the vertical direction is still regarded challenging. Processing on the length scale of a few tens of nanometers has nevertheless been demonstrated including processing of vertical nanowire transistors with a diameter of 10 nm. Besides logic applications, III-V MOSFETs hold promises in the area of millimeter-wave electronics.

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author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
in
74th Annual Device Research Conference, DRC 2016
volume
2016-August
publisher
Institute of Electrical and Electronics Engineers Inc.
conference name
74th Annual Device Research Conference, DRC 2016
external identifiers
  • scopus:84987754738
ISBN
9781509028276
DOI
10.1109/DRC.2016.7548411
language
English
LU publication?
yes
id
e8b7cd81-7fbe-4f2c-89d3-98dc32d4d068
date added to LUP
2016-12-02 14:06:41
date last changed
2017-01-01 08:41:34
@inproceedings{e8b7cd81-7fbe-4f2c-89d3-98dc32d4d068,
  abstract     = {<p>III-V MOSFETs are candidates for extension of the scaling roadmap beyond 10 nm. In the vertical direction, the requirements on gate-length scaling is less stringent and vertical III-V nanowire FETs are thus attractive for high density and low-power applications. While growth in the vertical direction allows flexibility in heterostructure combination and eases the path for integration on Si substrates, the processing in the vertical direction is still regarded challenging. Processing on the length scale of a few tens of nanometers has nevertheless been demonstrated including processing of vertical nanowire transistors with a diameter of 10 nm. Besides logic applications, III-V MOSFETs hold promises in the area of millimeter-wave electronics.</p>},
  author       = {Wernersson, Lars Erik},
  booktitle    = {74th Annual Device Research Conference, DRC 2016},
  isbn         = {9781509028276},
  language     = {eng},
  month        = {08},
  publisher    = {Institute of Electrical and Electronics Engineers Inc.},
  title        = {Vertical III-V nanowire MOSFETs, TFETs, and CMOS-Gates on Si : Processing in 3D},
  url          = {http://dx.doi.org/10.1109/DRC.2016.7548411},
  volume       = {2016-August},
  year         = {2016},
}