A Monolithic Digital Clock-Generator for On-Chip Clocking of Custom DSP's
(1996) In IEEE Journal of Solid-State Circuits 31(5). p.700-706- Abstract
- This paper shows a robust and easily implemented clock generator for custom designs. It is a fully digital design suitable for both high-speed clocking and low-voltage applications. This clocking method is digital, and it avoids analog methods like phase locked loops or delay line loops. Instead, the clock generator is based on a ring counter which stops a ring oscillator after the correct number of cycles. Both a 385 MHz clock and a 15 MHz custom DSP application using the on-chip clocking strategy are described. The prototypes have been fabricated in a 0.8 μm standard CMOS process. The major advantages with this clocking method are robustness, small size, low-power consumption, and that it can operate at a very low supply voltage
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/1033997
- author
- Nilsson, Peter LU and Torkelson, Mats LU
- organization
- publishing date
- 1996
- type
- Contribution to journal
- publication status
- published
- subject
- in
- IEEE Journal of Solid-State Circuits
- volume
- 31
- issue
- 5
- pages
- 700 - 706
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- external identifiers
-
- scopus:0030149831
- ISSN
- 0018-9200
- DOI
- 10.1109/4.509852
- language
- English
- LU publication?
- yes
- id
- eaafc2a4-c9f2-4a41-adb6-17d7f3756620 (old id 1033997)
- date added to LUP
- 2016-04-01 16:52:07
- date last changed
- 2022-01-28 22:44:50
@article{eaafc2a4-c9f2-4a41-adb6-17d7f3756620, abstract = {{This paper shows a robust and easily implemented clock generator for custom designs. It is a fully digital design suitable for both high-speed clocking and low-voltage applications. This clocking method is digital, and it avoids analog methods like phase locked loops or delay line loops. Instead, the clock generator is based on a ring counter which stops a ring oscillator after the correct number of cycles. Both a 385 MHz clock and a 15 MHz custom DSP application using the on-chip clocking strategy are described. The prototypes have been fabricated in a 0.8 μm standard CMOS process. The major advantages with this clocking method are robustness, small size, low-power consumption, and that it can operate at a very low supply voltage}}, author = {{Nilsson, Peter and Torkelson, Mats}}, issn = {{0018-9200}}, language = {{eng}}, number = {{5}}, pages = {{700--706}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, series = {{IEEE Journal of Solid-State Circuits}}, title = {{A Monolithic Digital Clock-Generator for On-Chip Clocking of Custom DSP's}}, url = {{http://dx.doi.org/10.1109/4.509852}}, doi = {{10.1109/4.509852}}, volume = {{31}}, year = {{1996}}, }