A low latency and area efficient FFT processor for massive MIMO systems
(2017) 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 p.1-4- Abstract
- A low-latency and area-efficient FFT/IFFT scheme is presented. The main idea is to utilize OFDM guard bands to reduce the operation counts and processing time, which results in 42% latency reduction compared to the reported pipelined schemes. To realize this idea, a modified pipelined architecture and an efficient data scheduling scheme are proposed. Furthermore, the proposed architecture is scalable to different FFT sizes and is also reconfigurable to support a wide range of applications. A 2048-point FFT/IFFT processor based on the proposed scheme has been designed, resulting in 1200 clock cycles latency, which can address the low latency demand of massive MIMO systems. Synthesis results in a 28 nm CMOS technology show that proposed... (More)
- A low-latency and area-efficient FFT/IFFT scheme is presented. The main idea is to utilize OFDM guard bands to reduce the operation counts and processing time, which results in 42% latency reduction compared to the reported pipelined schemes. To realize this idea, a modified pipelined architecture and an efficient data scheduling scheme are proposed. Furthermore, the proposed architecture is scalable to different FFT sizes and is also reconfigurable to support a wide range of applications. A 2048-point FFT/IFFT processor based on the proposed scheme has been designed, resulting in 1200 clock cycles latency, which can address the low latency demand of massive MIMO systems. Synthesis results in a 28 nm CMOS technology show that proposed design attains a throughput of 1 GS/s when clocked at 500 MHz. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/f617153a-f7fb-44ff-802d-dbbbffced025
- author
- Mahdavi, Mojtaba
LU
; Edfors, Ove LU
; Öwall, Viktor LU and Liu, Liang LU
- organization
- publishing date
- 2017-05-28
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- FFT, Massive MIMO, VLSI implementation, ASIC implementation, FPGA implementation, low latency, IFFT
- host publication
- IEEE International Symposium on Circuits and Systems (ISCAS), 2017 - Proceedings
- article number
- 8050692
- pages
- 4 pages
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
- conference location
- Baltimore, United States
- conference dates
- 2017-05-28 - 2017-05-31
- external identifiers
-
- scopus:85032703776
- ISBN
- 978-1-5090-1427-9
- 978-1-4673-6853-7
- DOI
- 10.1109/ISCAS.2017.8050692
- language
- English
- LU publication?
- yes
- id
- f617153a-f7fb-44ff-802d-dbbbffced025
- date added to LUP
- 2017-10-27 01:17:37
- date last changed
- 2025-01-22 03:10:24
@inproceedings{f617153a-f7fb-44ff-802d-dbbbffced025, abstract = {{A low-latency and area-efficient FFT/IFFT scheme is presented. The main idea is to utilize OFDM guard bands to reduce the operation counts and processing time, which results in 42% latency reduction compared to the reported pipelined schemes. To realize this idea, a modified pipelined architecture and an efficient data scheduling scheme are proposed. Furthermore, the proposed architecture is scalable to different FFT sizes and is also reconfigurable to support a wide range of applications. A 2048-point FFT/IFFT processor based on the proposed scheme has been designed, resulting in 1200 clock cycles latency, which can address the low latency demand of massive MIMO systems. Synthesis results in a 28 nm CMOS technology show that proposed design attains a throughput of 1 GS/s when clocked at 500 MHz.}}, author = {{Mahdavi, Mojtaba and Edfors, Ove and Öwall, Viktor and Liu, Liang}}, booktitle = {{IEEE International Symposium on Circuits and Systems (ISCAS), 2017 - Proceedings}}, isbn = {{978-1-5090-1427-9}}, keywords = {{FFT; Massive MIMO; VLSI implementation; ASIC implementation; FPGA implementation; low latency; IFFT}}, language = {{eng}}, month = {{05}}, pages = {{1--4}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{A low latency and area efficient FFT processor for massive MIMO systems}}, url = {{http://dx.doi.org/10.1109/ISCAS.2017.8050692}}, doi = {{10.1109/ISCAS.2017.8050692}}, year = {{2017}}, }