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A 0.7 to 3 GHz wireless receiver front end in 65-nm CMOS with an LNA linearized by positive feedback

Nejdel, Anders LU ; Törmänen, Markus LU and Sjöland, Henrik LU (2013) In Analog Integrated Circuits and Signal Processing 74(1). p.47-57
Abstract
This paper presents a wireless receiver frontend

intended for cellular applications implemented in a

65 nm CMOS technology. The circuit features a low noise

amplifier (LNA), quadrature passive mixers, and a frequency

divider generating 25 % duty cycle quadrature local

oscillator (LO) signals. A complementary common-gate

LNA is used, and to meet the stringent linearity requirements

it employs positive feedback with transistors biased

in the sub-threshold region, resulting in cancellation of the

third order non-linearity. The mixers are also linearized,

using a baseband to LO bootstrap circuit. Measurements of

the front-end show about 3.5 dB... (More)
This paper presents a wireless receiver frontend

intended for cellular applications implemented in a

65 nm CMOS technology. The circuit features a low noise

amplifier (LNA), quadrature passive mixers, and a frequency

divider generating 25 % duty cycle quadrature local

oscillator (LO) signals. A complementary common-gate

LNA is used, and to meet the stringent linearity requirements

it employs positive feedback with transistors biased

in the sub-threshold region, resulting in cancellation of the

third order non-linearity. The mixers are also linearized,

using a baseband to LO bootstrap circuit. Measurements of

the front-end show about 3.5 dB improvement in out-ofband

IIP3 at optimum bias of the positive feedback devices

in the LNA, resulting in an out-of-band IIP3 of 10 dBm.

With a frequency range from 0.7 to 3 GHz the receiver

front-end covers most important cellular bands, with an

input return loss above 9 dB and a voltage gain exceeding

16 dB for all bias settings. The circuit consumes 4.38 mA

from a 1.5 V supply. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
Positive feedback, Bootstrap passive mixer, Linearized receiver, RF, CMOS
in
Analog Integrated Circuits and Signal Processing
volume
74
issue
1
pages
47 - 57
publisher
Springer
external identifiers
  • wos:000312769900006
  • scopus:84871770377
ISSN
0925-1030
DOI
10.1007/s10470-012-9962-0
project
EIT_DARE Digitally-Assisted Radio Evolution
language
English
LU publication?
yes
id
fc10d5d9-8f9f-4643-924e-0191d6a94891 (old id 3054052)
date added to LUP
2012-09-18 12:22:02
date last changed
2019-04-23 02:22:08
@article{fc10d5d9-8f9f-4643-924e-0191d6a94891,
  abstract     = {This paper presents a wireless receiver frontend<br/><br>
intended for cellular applications implemented in a<br/><br>
65 nm CMOS technology. The circuit features a low noise<br/><br>
amplifier (LNA), quadrature passive mixers, and a frequency<br/><br>
divider generating 25 % duty cycle quadrature local<br/><br>
oscillator (LO) signals. A complementary common-gate<br/><br>
LNA is used, and to meet the stringent linearity requirements<br/><br>
it employs positive feedback with transistors biased<br/><br>
in the sub-threshold region, resulting in cancellation of the<br/><br>
third order non-linearity. The mixers are also linearized,<br/><br>
using a baseband to LO bootstrap circuit. Measurements of<br/><br>
the front-end show about 3.5 dB improvement in out-ofband<br/><br>
IIP3 at optimum bias of the positive feedback devices<br/><br>
in the LNA, resulting in an out-of-band IIP3 of 10 dBm.<br/><br>
With a frequency range from 0.7 to 3 GHz the receiver<br/><br>
front-end covers most important cellular bands, with an<br/><br>
input return loss above 9 dB and a voltage gain exceeding<br/><br>
16 dB for all bias settings. The circuit consumes 4.38 mA<br/><br>
from a 1.5 V supply.},
  author       = {Nejdel, Anders and Törmänen, Markus and Sjöland, Henrik},
  issn         = {0925-1030},
  keyword      = {Positive feedback,Bootstrap passive mixer,Linearized receiver,RF,CMOS},
  language     = {eng},
  number       = {1},
  pages        = {47--57},
  publisher    = {Springer},
  series       = {Analog Integrated Circuits and Signal Processing},
  title        = {A 0.7 to 3 GHz wireless receiver front end in 65-nm CMOS with an LNA linearized by positive feedback},
  url          = {http://dx.doi.org/10.1007/s10470-012-9962-0},
  volume       = {74},
  year         = {2013},
}