6 – 10 of 38
- show: 5
- |
- sort: year (new to old)
Close
Embed this list
<iframe src=" "
width=" "
height=" "
allowtransparency="true"
frameborder="0">
</iframe>
- 2012
-
Mark
Test Planning for Core-based 3D Stacked ICs under Power Constraints
2012) IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2012)(
- Contribution to conference › Paper, not in proceeding
- 2011
-
Mark
Scheduling Tests for 3D Stacked Chips under Power Constraints
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test Scheduling in an IEEE P1687 Environment with Resource and Power Constraints
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test Scheduling for 3D Stacked ICs under Power Constraints
2011) 2nd IEEE International Workshop on Reliability Aware System Design and Test (RASDAT)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias
2011) Swedish System-on-Chip Conference, SSoCC 2011(
- Contribution to conference › Paper, not in proceeding