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- 2011
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Mark
Test Scheduling in an IEEE P1687 Environment with Resource and Power Constraints
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
European Test Symposium (ETS) 2011
(
- Contribution to specialist publication or newspaper › Specialist publication article
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Mark
Scheduling Tests for 3D Stacked Chips under Power Constraints
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Level of Confidence Evaluation and Its Usage for Roll-back Recovery with Checkpointing Optimization
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Measurement Point Selection for In-Operation Wear-Out Monitoring
2011) 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS11)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test Planning for 3D Stacked ICs with Through-Silicon Vias
2011) Second IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits(
- Contribution to conference › Paper, not in proceeding
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Mark
A Study of Instrument Reuse and Retargeting in P1687
2011) IEEE Twelfth Workshop on RTL and High Level Testing (WRTLT 2011)(
- Contribution to conference › Paper, not in proceeding
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Mark
Study on the Level of Confidence for Roll-back Recovery with Checkpointing
2011) 1st Intl. Workshop on Dependability Issues in Deep-submicron Technologies (DDT 2011)(
- Contribution to conference › Paper, not in proceeding
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Mark
Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias
2011) Swedish System-on-Chip Conference, SSoCC 2011(
- Contribution to conference › Paper, not in proceeding
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Mark
SoC-Level Fault Management based on P1687 IJTAG
2011)(
- Other contribution › Miscellaneous