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- 2011
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Mark
Test Scheduling for 3D Stacked ICs under Power Constraints
2011) 2nd IEEE International Workshop on Reliability Aware System Design and Test (RASDAT)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Test Planning for 3D Stacked ICs with Through-Silicon Vias
2011) Second IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits(
- Contribution to conference › Paper, not in proceeding
-
Mark
A Study of Instrument Reuse and Retargeting in P1687
2011) IEEE Twelfth Workshop on RTL and High Level Testing (WRTLT 2011)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias
2011) Swedish System-on-Chip Conference, SSoCC 2011(
- Contribution to conference › Paper, not in proceeding
-
Mark
Study on the Level of Confidence for Roll-back Recovery with Checkpointing
2011) 1st Intl. Workshop on Dependability Issues in Deep-submicron Technologies (DDT 2011)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Test Scheduling and Test Access Optimization for Core-Based 3D Stacked ICs with Through-Silicon Vias: poster
2011) IEEE European Test Symposium (ETS), 2011(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2010
-
Mark
Optimizing Fault Tolerance for Multi-Processor System-on-Chip
2010)(
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
A Distributed Architecture to Check Global Properties for Post-Silicon Debug
2010) IEEE European Test Symposium (ETS'10), 2010(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Estimating Error-Probability and Its Application for Optimizing Roll-back Recovery with Checkpointing
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test Time Analysis for IEEE P1687
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding