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2012
Mark A 3.6mW, 90nm CMOS Gated-Vernier Time-to-Digital Converter with an Equivalent Resolution of 3.2ps
Lu, Ping ^LU ; Liscidini, Antonio and Andreani, Pietro ^LU (2012) In IEEE Journal of Solid-State Circuits 47(7). p.1626-1635
- Contribution to journal › Article
2011
Mark A 90nm CMOS Gated-Ring-Oscillator-Based Vernier Time-to-Digital Converter with Improved Resolution
Lu, Ping ^LU ; Andreani, Pietro ^LU and Liscidini, Antonio (2011) IEEE European Solid State Circuits Conference, ESSCIRC 2011 p.459-462
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding