Publications | Lund University Publications

1 – 3 of 3

show: 10
|
sort: year (new to old)

News feed Embed this list Save this search Mark all Export

Cancel

Embed this list

copy and paste the html snippet below into your own page:

<iframe src="https://lup.lub.lu.se/search/publication?embed=1&q=keywords+exact+%22Test+Time.%22&amp;hide_pagination=1&amp;hide_info=1&amp;hide_options=1"
  width="100%"
  height="400"
  allowtransparency="true"
  frameborder="0">
</iframe>

2014
Mark Test Planning and Test Access Mechanism Design for Stacked Chips using ILP
Sengupta, Breeta ^LU and Larsson, Erik ^LU (2014) IEEE VLSI Test Symposium (VTS) p.1-6
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
2012
Mark Test Planning for Core-based 3D Stacked ICs under Power Constraints
Sengupta, Breeta ^LU ; Ingelsson, Urban and Larsson, Erik ^LU (2012) IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2012)
- Contribution to conference › Paper, not in proceeding
2011
Mark Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias
Sengupta, Breeta ^LU ; Ingelsson, Urban and Larsson, Erik ^LU (2011) Swedish System-on-Chip Conference, SSoCC 2011
- Contribution to conference › Paper, not in proceeding