Fixed-point implementation of a robust complex valued divider architecture
(2005) European Conference on Circuit Theory and Design (ECCTD), 2005 p.143-146- Abstract
- In this paper a fixed-point implementation of robust complex valued divider architecture is presented. The architecture uses feedback loops and time multiplexing strategies resulting in a fast and area conservative architecture. The architecture has good numerical properties and the result is accurate to less than one ulp. A combination of low latency and high throughput rate makes the architecture ideal for modern high speed signal processing applications. The complex valued divider architecture was implemented and tested on a Xilinx Virtex-II FPGA, clocked at 100MHz, and can easily be ported to an ASIC. The FPGA implementation is used as a core component in a matrix inversion implementation
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/615897
- author
- Edman, Fredrik LU and Öwall, Viktor LU
- organization
- publishing date
- 2005
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- feedback loops, fixed-point implementation, ASIC, high speed signal processing applications, time multiplexing, 100 MHz, matrix inversion, Xilinx Virtex-II FPGA, complex valued divider architecture
- host publication
- [Host publication title missing]
- pages
- 143 - 146
- conference name
- European Conference on Circuit Theory and Design (ECCTD), 2005
- conference location
- Cork, Ireland
- conference dates
- 2005-08-28 - 2005-09-02
- external identifiers
-
- wos:000234406900036
- scopus:33749075210
- ISBN
- 0-7803-9066-0
- DOI
- 10.1109/ECCTD.2005.1522930
- language
- English
- LU publication?
- yes
- id
- 39f45ebf-6084-4a3a-b3f7-412e90c8db20 (old id 615897)
- date added to LUP
- 2016-04-04 13:23:35
- date last changed
- 2023-01-06 02:17:02
@inproceedings{39f45ebf-6084-4a3a-b3f7-412e90c8db20, abstract = {{In this paper a fixed-point implementation of robust complex valued divider architecture is presented. The architecture uses feedback loops and time multiplexing strategies resulting in a fast and area conservative architecture. The architecture has good numerical properties and the result is accurate to less than one ulp. A combination of low latency and high throughput rate makes the architecture ideal for modern high speed signal processing applications. The complex valued divider architecture was implemented and tested on a Xilinx Virtex-II FPGA, clocked at 100MHz, and can easily be ported to an ASIC. The FPGA implementation is used as a core component in a matrix inversion implementation}}, author = {{Edman, Fredrik and Öwall, Viktor}}, booktitle = {{[Host publication title missing]}}, isbn = {{0-7803-9066-0}}, keywords = {{feedback loops; fixed-point implementation; ASIC; high speed signal processing applications; time multiplexing; 100 MHz; matrix inversion; Xilinx Virtex-II FPGA; complex valued divider architecture}}, language = {{eng}}, pages = {{143--146}}, title = {{Fixed-point implementation of a robust complex valued divider architecture}}, url = {{http://dx.doi.org/10.1109/ECCTD.2005.1522930}}, doi = {{10.1109/ECCTD.2005.1522930}}, year = {{2005}}, }