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- 2017
-
Mark
Digital Phase Locked Loops for Radio Frequency Synthesis
2017)(
- Thesis › Doctoral thesis (monograph)
- 2016
-
Mark
A wide band fractional-N digital PLL with a noise shaping 2-D time to digital converter for LTE-A applications
(
- Contribution to journal › Article
-
Mark
GA optimized fuzzy controlled DPLL using discrete energy separation algorithm
2016) 1st IEEE International Conference on Control, Measurement and Instrumentation, CMI 2016 p.120-124(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2015
-
Mark
A 65nm CMOS fraction-N digital PLL with shaped in-band phase noise
2015) Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2013
-
Mark
Pebble games, proof complexity, and time-space trade-offs
(
- Contribution to journal › Article