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A wide band fractional-N digital PLL with a noise shaping 2-D time to digital converter for LTE-A applications

Mahmoud, Ahmed LU ; Andreani, Pietro LU and Lu, Ping LU (2016) In Analog Integrated Circuits and Signal Processing 89(2). p.337-345
Abstract

A wide band fractional-N digital PLL which uses a high resolution 2-dimension gated-Vernier time-to-digital converter (TDC) with 5.2 ps resolution is presented. The quantization noise shaping of the TDC greatly improves the in-band phase noise. While, in the same time, the 2-dimension structure makes the digital PLL (DPLL) be able to process large phase errors almost without the influence of latency time. Combined with a high figure-of-merit (FOM) class-D digitally controlled oscillator (DCO) and digital ΣΔ quantization noise cancellation based least mean square (LMS) algorithm, the DPLL achieves -110dBc/Hz and -140dBc/Hz for in-band and 10 MHz-offset phase noise, respectively, with carrier frequency of 3.5 GHz and 1 MHz bandwidth. The... (More)

A wide band fractional-N digital PLL which uses a high resolution 2-dimension gated-Vernier time-to-digital converter (TDC) with 5.2 ps resolution is presented. The quantization noise shaping of the TDC greatly improves the in-band phase noise. While, in the same time, the 2-dimension structure makes the digital PLL (DPLL) be able to process large phase errors almost without the influence of latency time. Combined with a high figure-of-merit (FOM) class-D digitally controlled oscillator (DCO) and digital ΣΔ quantization noise cancellation based least mean square (LMS) algorithm, the DPLL achieves -110dBc/Hz and -140dBc/Hz for in-band and 10 MHz-offset phase noise, respectively, with carrier frequency of 3.5 GHz and 1 MHz bandwidth. The digital PLL is simulated in a 65 nm CMOS process, consuming 11.2 mW from a 1.0 V supply.

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Please use this url to cite or link to this publication:
author
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
2-dimension, Cancellation, Class-D, DPLL, Gated, LMS, Noise shaping, Quantization noise, TDC, Vernier
in
Analog Integrated Circuits and Signal Processing
volume
89
issue
2
pages
9 pages
publisher
Springer
external identifiers
  • scopus:84976481106
  • wos:000387770900008
ISSN
0925-1030
DOI
10.1007/s10470-016-0786-1
language
English
LU publication?
yes
id
d15eed5e-a36c-4ae3-a045-ed8edf1f1e06
date added to LUP
2016-07-18 11:43:10
date last changed
2017-09-18 11:30:41
@article{d15eed5e-a36c-4ae3-a045-ed8edf1f1e06,
  abstract     = {<p>A wide band fractional-N digital PLL which uses a high resolution 2-dimension gated-Vernier time-to-digital converter (TDC) with 5.2 ps resolution is presented. The quantization noise shaping of the TDC greatly improves the in-band phase noise. While, in the same time, the 2-dimension structure makes the digital PLL (DPLL) be able to process large phase errors almost without the influence of latency time. Combined with a high figure-of-merit (FOM) class-D digitally controlled oscillator (DCO) and digital ΣΔ quantization noise cancellation based least mean square (LMS) algorithm, the DPLL achieves -110dBc/Hz and -140dBc/Hz for in-band and 10 MHz-offset phase noise, respectively, with carrier frequency of 3.5 GHz and 1 MHz bandwidth. The digital PLL is simulated in a 65 nm CMOS process, consuming 11.2 mW from a 1.0 V supply.</p>},
  author       = {Mahmoud, Ahmed and Andreani, Pietro and Lu, Ping},
  issn         = {0925-1030},
  keyword      = {2-dimension,Cancellation,Class-D,DPLL,Gated,LMS,Noise shaping,Quantization noise,TDC,Vernier},
  language     = {eng},
  number       = {2},
  pages        = {337--345},
  publisher    = {Springer},
  series       = {Analog Integrated Circuits and Signal Processing},
  title        = {A wide band fractional-N digital PLL with a noise shaping 2-D time to digital converter for LTE-A applications},
  url          = {http://dx.doi.org/10.1007/s10470-016-0786-1},
  volume       = {89},
  year         = {2016},
}