A Pipelined Loop-Unrolled SAR ADC with Open-Loop Amplification
(2025) EITM02 20252Department of Electrical and Information Technology
- Abstract
- This thesis presents the analysis and design of a three-stage pipelined loop-unrolled successive approximation register (Lu-SAR) analog-to-digital converter (ADC) implemented in 65 nm CMOS technology. The ADC is designed to achieve high speed and good linearity under low supply voltage and limited power, targeting wireless communication and high-speed data acquisition applications.
At the system level, inter-stage redundancy is used. The main non-idealities, including sampling distortion, comparator offset, capacitor mismatch, and open-loop amplifier nonlinearity, are analyzed and modeled. Open-loop residue amplifiers are adopted to improve speed and power efficiency, while digital background calibration is used to correct their gain... (More) - This thesis presents the analysis and design of a three-stage pipelined loop-unrolled successive approximation register (Lu-SAR) analog-to-digital converter (ADC) implemented in 65 nm CMOS technology. The ADC is designed to achieve high speed and good linearity under low supply voltage and limited power, targeting wireless communication and high-speed data acquisition applications.
At the system level, inter-stage redundancy is used. The main non-idealities, including sampling distortion, comparator offset, capacitor mismatch, and open-loop amplifier nonlinearity, are analyzed and modeled. Open-loop residue amplifiers are adopted to improve speed and power efficiency, while digital background calibration is used to correct their gain and nonlinearity errors.
A least-mean-square (LMS) based digital background calibration algorithm is developed to correct gain error, bit-weight deviation, and amplifier nonlinearity. Simulation results at both the behavioral and circuit level show that the proposed calibration can effectively restore the linearity. After calibration, the ADC achieves more than 60 dB SNDR and over 80 dB SFDR at 300 MS/s, which confirms the effectiveness of the proposed architecture and calibration scheme. (Less) - Popular Abstract
- Human civilization has always moved forward with new inventions. From the steam engines of the first industrial revolution to the spread of electricity, from the birth of computers to the rise of artificial intelligence (AI), each wave of innovation has changed how people understand and shape the world.
As technology developed, the way we handle information also changed from continuous analog signals, like sound or temperature, to digital signals made of zeros and ones. Together, these two types of signals form the foundation of the modern information world.
Today, AI is entering every corner of life: smart factories, self-driving cars, and medical devices all rely on collecting and understanding large amounts of data. To make this... (More) - Human civilization has always moved forward with new inventions. From the steam engines of the first industrial revolution to the spread of electricity, from the birth of computers to the rise of artificial intelligence (AI), each wave of innovation has changed how people understand and shape the world.
As technology developed, the way we handle information also changed from continuous analog signals, like sound or temperature, to digital signals made of zeros and ones. Together, these two types of signals form the foundation of the modern information world.
Today, AI is entering every corner of life: smart factories, self-driving cars, and medical devices all rely on collecting and understanding large amounts of data. To make this possible, we need a bridge between the real world and the digital world. This bridge is the analog-to-digital converter (ADC), a tiny but essential circuit that turns natural signals into numbers computers can understand.
This thesis explores a new ADC design that combines speed, accuracy, and low power. It also introduces a learning algorithm that helps the circuit automatically correct small internal errors.
By making this key interface more efficient and reliable, the work contributes to the technology that allows AI systems to sense and respond to the world more precisely and intelligently. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/student-papers/record/9215926
- author
- Xing, Shaobai LU
- supervisor
-
- Sijia Cheng LU
- organization
- course
- EITM02 20252
- year
- 2025
- type
- H2 - Master's Degree (Two Years)
- subject
- report number
- LU/LTH-EIT 2025-1104
- language
- English
- id
- 9215926
- date added to LUP
- 2026-06-03 12:44:46
- date last changed
- 2026-06-03 12:44:46
@misc{9215926,
abstract = {{This thesis presents the analysis and design of a three-stage pipelined loop-unrolled successive approximation register (Lu-SAR) analog-to-digital converter (ADC) implemented in 65 nm CMOS technology. The ADC is designed to achieve high speed and good linearity under low supply voltage and limited power, targeting wireless communication and high-speed data acquisition applications.
At the system level, inter-stage redundancy is used. The main non-idealities, including sampling distortion, comparator offset, capacitor mismatch, and open-loop amplifier nonlinearity, are analyzed and modeled. Open-loop residue amplifiers are adopted to improve speed and power efficiency, while digital background calibration is used to correct their gain and nonlinearity errors.
A least-mean-square (LMS) based digital background calibration algorithm is developed to correct gain error, bit-weight deviation, and amplifier nonlinearity. Simulation results at both the behavioral and circuit level show that the proposed calibration can effectively restore the linearity. After calibration, the ADC achieves more than 60 dB SNDR and over 80 dB SFDR at 300 MS/s, which confirms the effectiveness of the proposed architecture and calibration scheme.}},
author = {{Xing, Shaobai}},
language = {{eng}},
note = {{Student Paper}},
title = {{A Pipelined Loop-Unrolled SAR ADC with Open-Loop Amplification}},
year = {{2025}},
}