RTL Restructuring Methodology to Overcome Physical Design Challenges in Complex IPs

Abstract

The continued scaling of complementary metal-oxide semiconductor (CMOS) technology has fundamentally altered the relationship between register-transfer level (RTL) design and physical implementation in application-specific integrated circuits. The traditional sequential treatment of these two activities is no longer adequate for meeting the power, performance, and area targets of modern system-on-chip designs, resulting in costly iterations between the frontend and backend design teams that are often compounded by manually executed RTL restructuring without formal validation.

This thesis develops a robust and validated RTL restructuring methodology that addresses this misalignment. The methodology is structured into three sequential phases covering physically-aware RTL and collateral restructuring, formal validation, and re-implementation with comparative metric analysis. Two complementary flows are derived from it, that is, a Backend Partitioning Flow targeting the physical design and integration team, which constitutes the primary contribution of the work, and a Frontend Design Exploration Flow targeting the RTL and IP design teams.

The methodology is applied to two complex industrial intellectual property (IP) blocks. The first investigation, on an Ethernet Switch IP characterized by a large IO count, long tool runtimes, and heavy pin congestion, demonstrates the flow’s ability to support the discovery of new partitioning solutions. The second investigation, on a CPU IP and an Interconnect IP, demonstrates the flow’s ability to rapidly and reliably apply a known partitioning solution by merging the two IPs into a single combined partition. The merged partition matches the better of the two original partitions on worst-case timing slack while substantially resolving the timing problems of the more problematic partition, at the cost of an expected increase in tool runtime, with functional correctness preserved as confirmed by formal logic equivalence checking. Both investigations compress restructuring efforts that would typically require weeks of manual engineering work into a matter of hours. The first investigation additionally revealed restructuring scenarios that fell outside the scope of the available EDA tooling, and an AI-supported restructuring approach was explored as a complement to the methodology, delivering substantial improvements in IO count and runtime on the same design.

Popular Abstract

The hidden city inside every chip – and how to redesign it faster

Every modern chip goes through a slow, error-prone reorganization before it can be built. This thesis shows how to do that work in hours instead of weeks, and prove the chip still does exactly what it should.

Think of designing a chip a little like designing a city. One team decides what the city needs, such as homes, shops, hospitals, and roads between them. Another team has to fit all of that onto an actual piece of land, with real distances, real traffic, and real limits. The first team works on paper. The second team has to make it work in reality.

For a long time, this division of labor worked. But the chips inside today’s phones, cars, base stations, and data centres have become so dense that the two views no longer line up. Plans that look perfectly sensible on paper turn out to be impossible to lay out neatly on the silicon. Signals end up taking the long way around. Regions get too crowded for everything to fit. Connections that need to be fast are too slow. The chip simply does not behave the way it was meant to.

The only fix is to go back and reorganize the original plan with the physical reality in mind. Traditionally, engineers do this by hand. It takes days or weeks. It is easy to break things by accident. And it has to happen again and again before the chip is ready. Every round delays the chip’s journey to production, and these days, the world is waiting on a lot of chips.

This thesis builds a structured way of doing that reorganization. Specialized software handles the changes. A mathematical check then proves that the reorganized chip does exactly the same job as the original. Not “probably the same”, but the same, with certainty. The result is a process that turns weeks of careful manual work into a matter of hours.

The method was tried on two real industrial designs. One was a piece of networking hardware whose design runs had grown painfully long and whose connections to the rest of the chip had become unmanageable; reorganizing it cut the design time by roughly a third. Another was a pair of large blocks that struggled to talk to each other across the seam between them. Merging them into one dramatically improved how reliably the chip could keep up with its own clock.

There was one surprise. For some of the trickiest reorganization steps, the specialized software simply could not cope. An AI coding assistant was brought in to handle those bits, and every change it made was checked, mathematically, before being accepted. It worked. The AI did not replace the engineering tools. It filled in the gaps they could not reach.

Chips will only keep getting denser. The kind of work described here is quietly becoming essential to keeping the silicon behind every connected device on time, and getting it right the first time.

• author: Sajeeth Mohan, Rahul
• supervisor: Liang Liu
• organization: Department of Electrical and Information Technology
• alternative title: Metodik för RTL-omstrukturering för att hantera fysikaliska designutmaningar i komplexa IP-block
• course: EITM02 20261
• year: 2026
• type: H2 - Master's Degree (Two Years)
• subject: Technology and Engineering
• keywords: RTL Restructuring, Physically-Aware Design, Hierarchical Partitioning, Logic Equivalence Checking, Timing Closure, ASIC Design Flow
• language: English
• additional info: The work was carried out at Ericsson AB in Stockholm within the ASIC SoC Backend and Integration Team.
• id: 9233982
• date added to LUP: 2026-06-10 11:35:54
• date last changed: 2026-06-10 11:35:54